Click on the image of the package family of interest for dimensioned drawings of common pin counts.

For detailed PCB layout drawings click here to go to the Semiconductor Vendor Links page on RF Cafe. See table of package information at bottom of page.

DIP (Dual Inline Package)	SOIC (Small Outline Integrated Circuit)
PLCC (Plastic Leaded Chip Carrier)	LCC
TO (Transistor Outline)	TSSOP (Thin Shrink Small Outline Package)
SOT (Small Outline Transistor)	SSOP (Shrink Small Outline Package)

Small Package Designations
Designation	Package
DIP	Dual inline package
MSOP	Micro SOP
PDIP	Plastic DIP
QSOP	Quarter SOP
SIP	Single inline package
SOIC (or SO)	Small-outline IC
SOJ	J-lead SOP
SOP	Small-outline package
SOT	Small-outline transistor
SSOP	Shrink SOP
TSOP	Thin SOP
TSSOP	Thin shrink SOP
TVSOP	Thin very fine SOP
Note: These designations are often followed by numbers that indicate the number of leads.

Small Package Dimensions
Package designation and pin count	Nominal body size (L3W3H) (mm)	Total footprint (L3W) (mm)	Lead pitch (mm)
DIP-8	10×6×5	5×7.5	2.54 (0.1 in.)
SO-8	5×4×1.75	5×6	1.27 (0.05 in.)
SSOP-8	3×5.3×2	3×8	0.65
TSSOP-8	3×4.4×1.2	3×6.4	0.65
MSOP-8	3×3×1.1	3×5	0.65
TVSOP-14	3.6×4.4×1.2	3×6.4	0.4
QSOP-16	4.9×3.9×1.7	4.9×6	0.635 (0.025 in.)
SOT23-5	3×1.6×1	3×3	0.95