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Note: Many answers contain passages quoted in whole or in part from the text.
quiz is based on the information presented in Substrate Noise Coupling in Analog/RF Circuits, by Stephane
Bronkers, Geert Van der Plas, Gerd Vandersteen, and Yves Rolain. Published by Artech House.
Some of these books are available as prizes in the monthly
RF Cafe Giveaway.
1. Which is NOT a class of substrate noise analysis?
2. What is the most popular and straightforward
method for shielding analog integrated circuits
against substrate noise?
a) Ground plane
c) Copper conductors
d) Metal shields
3. Aggressor and victim refer to what process?
a) The design process and
engineer doing the design, respectively
b) The source of and recipient of substrate noise, respectively
c) Hole and electron conduction, respectively
d) Conductor and insulator substrate noise, respectively
4. What is the best way to separate substrate coupling noise from other regional
sources when developing mixed (digital/analog) signal devices?
a) Dice between the
regions to physically separate the digital/analog regions, then wire bond between
b) Process a neutral region
between digital / analog regions, then wire bond between
c) Process a solid vertical metal wall between
digital/analog regions, then wire bond between
d) There is no method for totally separating substrate noise
5. At high frequencies, which off-chip noise coupling mechanism
a) Capacitive coupling between PCB traces
b) Inductive coupling between PCB
c) Resistive coupling between the PCB and the die
d) Magnetic coupling between die bond wires
6. What is the primary source of FM modulated noise spurs?
a) Doping impurities
b) Heavy p-type doping
c) Perturbations on the ground interconnect
d) Low resistivity passivation
7. In a VCO circuit, what is a likely mechanism
for AM spur generation and intermediate frequencies?
a) Capacitive coupling from on-chip inductors to the
b) Inductive coupling from on-chip inductors to the substrate
c) Magnetic coupling from on-chip
inductors to the substrate
d) Resistive coupling from on-chip inductors to the substrate
8. How are digital and analog grounds kept separate on the die?
large resistors between digital / analog regions
b) Integrate large inductors between digital / analog regions
c) There is no effective method for separating digital / analog grounds
d) Separate digital / analog ground
metal on the die, with separate off-chip digital / analog
For what purpose is parasitic extraction used?
a) Obtaining parasitic current / voltage values for use in
b) Obtaining parasitic RLC values for publication in user datasheets
parasitic RLC values for use in simulation
d) Obtaining parasitic current / voltage values for use in
10. What determines to a large extent the efficiency of a P+
a) Impedance of the ground interconnect
b) P-type doping density
c) Passivation purity
d) Voltage filtering
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