Zahra sadat Ebadi
5622 Montgomery Place,
Vancouver, BC Canada V6T 2C7
Phone: (604) 221-5162
Email: zahra@ece.ubc.ca

Objectives
To obtain a challenging research and development position in RF electronics. Analog/RF IC design, high frequency circuits and related fields are of interest. Working in a multidisciplinary environment has improved my technical skills and leadership abilities, helping me to undertake broad range of responsibilities.

Work Experience
• Research Assistant, UBC, Vancouver, Canada, 2003-2005
o Developed a receiver’s RF front-end for IEEE 802.11g using 0.18μm CMOS
o Designed and simulated LNAs, mixers, VCOs and amplifiers using CMOS
o Designed and developed high and low-frequency customized PCB boards
o Developed measurement strategies and characterization of RF front-ends
o Experienced with high frequency measurement equipment
o Developed a system-level compensation technique for Zero-IF receivers
o Applied DSP processing for receivers to compensate front-end non-idealities
o Gained deep knowledge of various receiver architectures
• IC Design Engineer, KavoshCom, Tehran, Iran, 2006
o Designed and taped out RF blocks of low power GPS receiver
• Teaching Assistant, UBC, Vancouver, Canada, 2001-2005
o Prepared lecture notes and assignments for VLSI courses
o Managed students in the Electronic circuits II laboratory
• Research Assistant, UBC, Vancouver, Canada, 2001-2003
o Developed a novel methodology for Test Access Mechanism for SoCs
o Developed a methodology for optimized wrapper design for IP cores
• Electronic Design Engineer, Donya-ye-pardazesh Co., Tehran, Iran, 1998
o Designed and implemented a fast EPROM copier circuit (board design)

Technical Skills
• Solid background in RF and analog IC design and receiver system design
• Design Tools: Cadence, ADS, Hspice, MAGIC, IRSIM, and PCB design (Protel)
• Fast learner with problem solving skills to work independently/team member
• Solid background in heuristic algorithms (e.g., genetic algorithms)
• Programming languages: Matlab/Simulink, C/C++ and Java; Scripting: Perl

Zahra sadat Ebadi

Education
• University of British Columbia, Vancouver, BC, Canada.
Ph.D. in Electrical and Computer Engineering, August 2007 (expected).
Thesis title: Application of complex quantized feedback in direct conversion receiver for wireless applications
• University of British Columbia, Vancouver, BC, Canada.
M.A.Sc. in Electrical and Computer Engineering - VLSI, January 2003.
GPA: 90.5 (A+). Thesis title: Optimum test strategy for SoCs: wrapper and TAM design and optimization
• Sharif University of Technology, Tehran, Iran.
B.A.Sc. in Electrical Engineering - Electronics, January 2000.
GPA: 3.3/4.00 (A). Thesis title: Applications of genetic algorithm in electrical engineering

Honors and Awards
• NSERC Canada Graduate Scholarship (CGS-D), UBC, Canada, 2005-2007
• University Graduate Fellowship (UGF), UBC, Canada, 2004-2005
• Full undergraduate tuition waiver, Sharif University of Technology, Iran, 1995- 2000
• Ranked 30th in 1,000,000 participants in the B.A.Sc national entrance exam, Iran, 1995
Selected Publications
• Z. S. Ebadi, R. Saleh, “Adaptive compensation of RF front-end nonidealities in direct conversion receiver”, submitted to IEEE Transactions on Circuits and Systems II, 2007.
• Z. S. Ebadi, R. Saleh, “CMOS direct conversion receiver design issues, a tutorial”, submitted to Integration- the VLSI, special issue on AMS/RF CMOS circuit design for wireless transceivers, 2007.
• Z. S. Ebadi, R. Saleh, “Reconfigurable RF front-end for IQ mismatch compensation”, in preparation (50% complete), IEEE Journal on Solid States, 2007.
• Z. S. Ebadi, S. Mirabbasi, R. Saleh, “The application of complex quantized feedback in integrated wireless receivers”, IEEE Transactions on Circuits and systems, Vol. 53, No. 3, pp. 594-604, March 2006.
• Z. S. Ebadi, A. N. Avanaki, A. Ivanov and R. Saleh, “Design and implementation of reconfigurable and flexible TAM for SoC”, Integration- the VLSI journal, Vol. 40, No. 2, pp. 149-160, 2006.
• Z. S. Ebadi, A. Ivanov, “Time domain multiplexed TAM: implementation and comparison”, Proc. of Design, Automation and Test in Europe, pp. 732-737, 2003.
• Z.S. Ebadi, A. Ivanov, “Design of an optimal test access architecture under power and place-and-route constraints using GA”, Proc. of IEEE Latin-American Test Workshop, pp. 154-159, 2002.
• Z.S. Ebadi, A. Ivanov, “Design of an optimal test access architecture using genetic algorithm”, Proc. of IEEE Asian Test Symposium (ATS), pp. 205-210, 2001.