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SUBRAMANIAN ANANTHANARAYANAN
Phone: 817-584-4119 Email: asub85@gmail.com OBJECTIVE Self-motivated, detail oriented Electrical Engineer currently pursuing MSEE, looking to secure an internship position in a competitive environment where I could leverage my excellent leadership and communication skills to add value to the organization. ACADEMIC DETAILS Master of Science in Electrical Engineering 12/2008 (Expected)
University of Texas, Arlington, TX CGPA: 3.0/4
Bachelors in Electrical and Electronics Engineering 04/2007
Anna University, INDIA CGPA: 3.7/4 TECHNICAL SKILL SUMMARY Programming Languages: C, MATLAB 7.1, Cimplicity, Perl
Simulators: LabVIEW, PSPICE, Cadence
Operating Systems: Windows NT/XP/VISTA, Mac OS, UNIX
Packages Microsoft Office Tools, Visual Studio
Database Microsoft Access
Area of Interest UMTS, GSM, CDMA, TDMA, Bluetooth, 802.11 COURSES UNDERTAKEN INTERNSHIP Digital VLSI Design, and RFIC Design for wireless communication, MEMS, Wireless Communication, Advanced Electronics, Digital Signal Processing, Linear systems engineering. INTERNSHIP Automation and Control Systems, Pune (India) July2006
Where the application of PLC & AC Drives were incorporated into real world systems.
Tata Motors, Ltd.(India) January2007
The project deals with the reconditioning of a Robocar using GE FANUC - CIMPLICITY
Follett Corporation(UTA Bookstore), Arlington, TX July 07 - Present
Working as a sales associate in the Supplies Department
Assist customers by answering questions and phone calls, providing directions, maintaining stock and inventory, tagging merchandise, itemizing and totaling customers purchases.
PROJECTS Wireless Modem Design:
System level design for a mobile satellite based wireless user terminal using block phase estimation algorithm.
Design a simulation reference system for a Rician Flat Fading channel using MATLAB 7.1
Design a demodulator for the same channel with QPSK modulation Design of VCO (Voltage Controlled Oscillator) for WCDMA & WLAN standards
Designed a VCO for a frequency of 2.4 GHz using Cadence tools
Calculated phase noise for the same using Cadence Spectre-RF
Inductor modeling was done using ASITIC Design of LNA (Low Noise Amplifier) for Bluetooth applications
Designed a LNA for a frequency of 2.4 GHz using Cadence tools
Parametric Analysis, Noise Figure and Gain Analysis were carried out using Cadence Spectre-RF Design of Phase Locked Loop for GSM standard
Designed a phase locked loop that can operate for an input frequency of 200 MHz.
Parametric Analysis, Noise Figure and Gain Analysis were carried out using Cadence Spectre-RF
Design of a 16 bit Synchronous DRAM
Developed a transistor level design of a 16 bit Synchronous DRAM (SDRAM)
Used TSMC process with a 0.25 um technology. |