MAHESH ARKALGUD SHIVAKUMAR
Mobile: 9886577992 / Email: mahesh_a_shivakumar@yahoo.co.in
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Career Vision: Job/Assignments in Design and Verification in the field of FPGA/ASIC/SoC
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PROFESSIONAL PROFILE

■ 1.9 years of experience in RTL Coding and Verification for Altera and Xilinx FPGA’s based designs.
■ Experience in implementaion of RFID, VoIP protocols and DSP algorithiums from C into Verilog.
■ Used common firmware protocols like SPORT, SPI, PCI, and RS232 for designs.
■ Expertise in Verilog and VHDL coding.
■ Experience in Simulation, Synthesis and Place & Route for the FPGA based designs using Altera Quartus II 7.1, Xilinx ISE6.3 and ModelSim tools.
■ Currently working as VLSI Engineer in R&D team at CEM Solutions, Bangalore.
■ Done Masters of Engineering in Microelectronics from RMIT University, Melbourne, Australia.

TECHNICAL SKILL SET

Microelectronic Engineering Skill set
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Hardware Description Language: Verilog, VHDL and SystemVerilog.
EDA Tools: Altera Quartus II 7.1, Xilinx ISE6.3, ModelSim, Synopsys DC-Shell for ASIC synthesis and Cadence virtuoso/Analog Artist.

Computer software skills
________________________________________Programming Languages: C, C++.
Scripting Languages: Tcl.
Operating Environment: Microsoft Windows family, Linux, UNIX, Sun Solaris and DOS.

WORK EXPERIENCE

Company #1

Name of the company
Clarinox Technologies Ltd, Melbourne, Australia. (www.clarinox.com)
Position Electronics Engineer
Period worked 8 Months (Mar’06 – Oct’06 )
Company Profile Clarinox Technologies is an innovative Australia based company, their focus into development of a wireless embedded device.

Company #2

Name of the company
CEM Solutions, Bangalore, India. (www.cem-solutions.net)
Position VLSI Engineer.
Period worked 1.1 year (Mar ’07 – Till date )
Company Profile CEM is an end-to-end telecom product provider, specializing in next generation telecom technologies. Their products are for voice over Ip communication, Video over Ip communication, Broadcast over Ip.

ACADAMIC PUSUITE

2006 M.E (Microelectronics), RMIT University, Melbourne, Australia. (GPA 3/4)72.65%
2003 B.E (E&C), Visvesvaraya University, SIT, Tumkur, India. 69.00%
1999 II PUC, Government First Grade Science College, Hassan, India. 82.43%

PROJECTS UNDERTAKEN

Project: 256 Channel Echo Canceller for 32 ms tail (Verilog).
• Duration: Jan’08 – Till date
• Tools/Resources used: Altera Quartus II 7.1 for FPGA, ModelSim.
• Summary: The echo cancelletion for 256 channels is done using Pin - Pong buffer logic and using SDRAM. In pinpong logic, six 16 bit widths and 256 depth of onchip memory is used in two sets of three each as per odd channel and even channel. At any instant one set of data in onchip memory is will processed for echo cancellation, while other set of onchip memory will loaded with the data from SDRAM.
Architecture of 256 channels consists of modules, like an echo canceller, sdram interace, timing and contro unit, sdram controller and additional gluelogic to do echo cancelletion of 256 channels.
• Company: CEM Solutions, Bangalore, India.
• My Role:
• RTL design in Verilog.
• Chip block architecture and block specification for design implementation
• Design of finite state machines, data and control interface blocks
• Chip block verification planning and implementation
• Design syntheses, defining and meeting timing constraints
• Chip design validation at board level (ALTERA DE2 board).

Project: Echo Canceller for 32 ms tail (Verilog).
• Duration: Oct’07 – Jan’08
• Tools/Resources used: Altera Quartus II 7.1 for FPGA, ModelSim.
• Accomplishments: Expertise in implementation of algorithium from C into Verilog.
• Summary: Echo Canceller implemeted using 256 taps to do echo cancellation for 32 ms, this echo cancellation is done using dual path algorithium. 256 samples of tx is stored in onchip memory of FPGA. For every new sample received, coefficients are calculated using LMS algorithium. New simulated echo value is caluculated using both forground and background coefficient by FIR filter method. The calculated echo is cancelled from the rx sample and echo clean sample is sent for non linear processing (NLP).
• Company: CEM Solutions, Bangalore, India.

Project: SDRAM Controller (IC42S16400-7T) (Verilog).
• Duration: Aug’07 – Oct’07
• Tools/Resources used: Altera Quartus II 7.1 for FPGA, ModelSim.
• Accomplishments: Expertise in Verilog coding.
• Summary: At power on SDRAM Controller intializes the SDRAM with series of command like NOP, AUTO REFRESH, and PRECHARGE and then it programs the mode register to indicate write and reading mode, wrap type and latency of SDRAM and then it is in user mode, where data is either writen or read in full page and single read and write mode by following series of command.
• Company: CEM Solutions, Bangalore, India.

Project: Glue logic for VOIP Card for 16 - channel (Client project: - BPL) (Verilog).
• Duration: Jun’07 – Aug’07
• Tools/Resources used: Altera Quartus II 7.1 for FPGA, ModelSim.
• Accomplishments: Expertise in Verilog coding.
• Summary: The signalling and data between private branch exchange(PBX) and Index Sigma for 16 channel is received through backplane, SPORT interface used to interface with backplane of PBX side and and also towards Index side, while SPI interface is used to interface with PMCSiera Processor. This project was done in two modes, first mode was dynamic mode and another mode is static mode and the device used is Cyclone II FPGA (EPC35F672C6).
• Company: CEM Solutions, Bangalore, India.

Project: Audio codec implementation for 16 bit into 8-bit Alaw and Ulaw (Verilog).
• Duration: May’07 – Jun’07
• Tools/Resources used: Altera Quartus II 7.1 for FPGA, ModelSim.
• Accomplishments: Profiency in implementing algorithium from C into Verilog for MAX II CPLD.
• Summary: Implementation of algorithm for coding a 16-bit linear source sample down to an 8-bit Ulaw and Alaw sample, and decoding a 8-bit Alaw and ulaw sample into an 16-bit linear sample in Verilog HDL.
• Company: CEM Solutions, Bangalore, India.

Project: Glue logic for 4- port PCI Interface Card (Verilog).
• Duration: Mar’07 – May’07
• Tools/Resources used: Altera Quartus II 7.1 for FPGA, ModelSim.
• Accomplishments: Expertise in Classic timing Analyser, ALTERA Quartus II 7.1 and Verilog.
• Summary: Glue logic interface between PCI 9030, a 32-bit, 33-MHz PCI Bus Target Interface chip with A4 die of Dallas 21Q352 transceiver chip for T1/E1 line. I was assinged to design RAMB4_S1_16, RAMB4_S1_32 (dual port RAM) in verilog HDL using dual clock onchip memory, functional and timing verification of the glue logic for serial loop back and parrallel loop back mode of operation and the device used is Cyclone II FPGA (EPC35F672C6).
• Company: CEM Solutions, Bangalore, India.

Project: Transmitter Block of Vicinity Coupling Device for RFID (VHDL).
• Duration: July’06 – Oct’06
• Tools/Resources used: Xilinx ISE6.3 for FPGA, ModelSim.

• Accomplishments: Expertise in VHDL coding.
• Summary: Transmitter block of VCD transmits command to VICC’s. Data is transmitted either in 1 out of 256 method of coding or in 1 out 4 coding method with high data rate or low data rate between frame delimiters SOF and EOF. SOF is different for each coding method of data transmission, while the EOF frame is same for both the coding method.
• Company: Clarinox Pty Ltd, Melbourne, Australia.

Project: Receiver Block of Vicinity Coupling Device for RFID [Radio Frequency Identification Device] (VHDL).
• Duration: Mar’06 – July’06
• Tools/Resources used: Xilinx ISE6.3 for FPGA, ModelSim.
• Accomplishments: Expertise in VHDL coding.
• Summary: The receiver block of VCD (Vicinity Coupling Device) receives the response of VICC’s for particular command transmitted, the received data is delimited by frame limiters SOF (Start of Frame) and EOF (End of Frame), data reception will be either in high data rate or low data rate and is coded using one subcarrier method or two subcarrier method of coding. The decoded response of VICC is then transferred into FIFO.
• Company: Clarinox Pty Ltd, Melbourne, Australia.
Recognition for Studious Excellence;

 Best Project of the Year award for major project “E-Host” carried during bachelor’s degree.
 Won prizes for technical presentations in inter-college competitions during bachelor’s degree.
 Volunteered & served on various technical committees during academic career.
 Member of Australian Microelectronics Network, Member of IEEE and Member of Green Earth Club.

PERSONAL DETAILS
Date of Birth 09-03-1982
Address 76/79.N1 Ground Floor, II Main, II stage, Chikka Lakshmi Layout, Koramangala Bangalore.