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How the J-K Flip-Flops
January 1969 Radio-Electronics Article

January 1969 Radio-Electronics

January 1969 Radio-Electronics Cover - RF Cafe[Table of Contents]

Wax nostalgic about and learn from the history of early electronics. See articles from Radio-Electronics, published 1930-1988. All copyrights hereby acknowledged.

An alternate title for this article that appeared in a 1969 issue of Radio-Electronics magazine could have been, "How to Build a J-K Flip-Flop." Author Leonard Geisler takes the reader through a step-by-step assembly of a functional J-K flip-flop using a collection of 1- 2- and 3-input NAND gates. The 1-input NAND, in case you are wondering, is used as an inverter. The piece reads like an in-depth first-semester electrical engineering technician course textbook. In the process of building the J-K, an R-S (reset/set) flip-flop is described. Nowhere does Geisler offer an explanation of from where the "J" and the "K" input labels come. According to electrical engineer Sourav Bhattacharya blog, it was Dr. Eldred Nelson of Hughes Aircraft who first coined the term J-K flip-flop. "Flip-flops in use at Hughes at the time were all of the type that came to be known as J-K. In designing a logical system, Dr. Nelson assigned letters to flip-flop inputs as follows: #1: A & B, #2: C & D, #3: E & F, #4: G & H, #5: J & K. Given the size of the system that he was working on, Dr. Nelson realized that he was going to run out of letters, so he decided to use J and K as the set and reset input of each flip-flop in his system (using subscripts to distinguish the flip-flops), since J and K were 'nice, innocuous letters.' Nelson used the notations 'j-input' and 'k-input' in a patent application filed in 1953." And now you know... the rest of the story (hat tip to Paul Harvey for his trademark story ending).

How the J-K Flip-Flops

Four steps to understanding a useful IC logic device.

By Leonard E. Geisler*

Q1 is at saturation, holding NAND off - RF Cafe

Fig. 1 - With one or both inputs grounded, Q1 is at saturation, holding NAND off.

Basic logic circuits such as the AND, OR and NOT operate without memories. The AND circuit, for example, will provide a logic ONE output only when all inputs to the circuit are also logic ONE simultaneously. Otherwise, the circuit remains in a logic ZERO state.

Logic circuits that can be placed in either of two stable states and "remember" this state until switched to another are called bistable or flip-flop.

In various combinations these bistable circuits form register, counter, storage and other essential digital circuitry. The J-K flip-flop described is ideal for counting and divider circuits since it has one output pulse for each two input pulses.

Basic NAND Circuit

Study the circuit diagram of the basic two-input NAND element (Fig. 1). Assume input terminals a and b are at ground potential; Q1's base is tied to B+ through a biasing resistor, causing forward bias as long as one or both input terminals are grounded. The forward bias applied to Q1's base causes Q1 to go into saturation, grounding Q2's base. (Q1 cannot draw much collector current because of the very high reverse base-collector resistance, R1, internal to Q2.)

With Q2 cut off because of the ground level at its base, its collector potential rises toward B+ and its emitter potential falls to ground. Transistor Q3's base, tied to Q2's collector, sees the positive rise in potential; Q3 saturates, carrying terminal c toward B+. At the same instant Q4 sees virtual ground potential and cuts off. If either of the input terminals is raised from ground, Q1 operating conditions do not change. But if both input terminals are raised from ground, Q1 cuts off and the current previously flowing through the base-emitter diode in Q1 now flows through the base-collector diode path to Q2's base, causing Q2 to saturate.

As Q2 saturates, its collector potential drops toward ground and its emitter potential rises toward B+. Transistor Q2's ground-going collector potential causes Q3 to cut off. Now Q2's rising emitter potential pulls Q4 into saturation (Q4 draws collector current from B+ through an external load), and Q4's collector potential drops to virtually ground level.

In computer designer jargon, a ground-level signal is usually called "logic ZERO" and a high-level signal is called "logic ONE." To simplify descriptions, the ZERO condition at an input or output terminal is signified by a bar above the terminal designator. Thus, a means that terminal a is at virtual ground level (or logic ZERO). Absence of the bar indicates the signal input is at the high level (or logic ONE). In Boolean algebra, the input conditions required for a NAND to produce either a high (logic ONE) or low (logic ZERO) output can be shown in the following formulas:

(ab ) + (a • b) + (ab) =c (1)

and

a • b = c (2)

Note that only (2) above produces a logic ZERO output. The dot signifies "and" and the plus sign "or."

Two NANDs make a flip-flop

Two NAND elements connected as shown make a set-reset (RS) flip-flop - RF Cafe

Fig. 2 - Two NAND elements connected as shown make a set-reset (RS) flip-flop.

two more NANDs will provide for clock-pulse sync of the RS flip-flop - RF Cafe

Fig. 3 - Addition of two more NANDs will provide for clock-pulse sync of the RS flip-flop. Flip-flop toggles whenever clock pulse occurs simultaneously with data pulse.

To produce a simple "set-reset" flip-flop, two two-input NANDs are connected as shown in Fig. 2. The cross coupling insures that the flip-flop will toggle (change states) only when the correct input conditions are present.

For example, assume that NAND 2N1's output is high and NAND 2N2's output is low (this is indicated in the figure by numeral 1 next to terminal c of 2N1 and θ next to 2N2 terminal c). What conditions exist at the input terminals to produce the outputs shown?

By examining the formulas and the flip-flop logic diagram we conclude that 2N2 must have terminals a and b high for a ZERO output, satisfying formula (2). In practice, 2N1's terminal a is also high; both inputs are high at all times except when the flip-flop is toggled to the other state by momentarily grounding the appropriate input terminal.

Clocked RS Flip-Flop

The simple set-reset (RS) flip-flop is used generally where simple pulse-train counting or frequency dividing is required without regard to either output state or synchronism with other pulses in a system. For more precise applications two more NANDs are added to the RS flip-flop (Fig. 3), and one input is tied each to a clock-pulse source.

Now when the clock pulse occurs while either input is being pulsed, the flip-flop toggles (provided, of course, the set or reset pulse is applied to the side opposite the one which is high). Note that addition of the two NANDs reverses the sign of the activating pulses; now a positive-going pulse is required to toggle the flip-flop.

By adding another input to the NAND flip-flop elements of Fig. 3 (removing the two-input NANDs and substituting two three-input NANDs), the clocked flip-flop (Fig.  4), is improved considerably since the output can be set or reset to a desired state before starting the counting operation. This means, for example, a count can always be started at zero, or a given quantity can be counted or recorded, and the counter can then be reset to zero for the next counting operation.

J-K Flip-Flop

All the flip-flops described have one common failing: they can be tricked into "racing" or dithering between states if both signal inputs are pulsed simultaneously. The J-K flip-flop has been developed to correct such a problem (Fig. 5). Adding another flip-flop to the circuit in Fig. 4 makes a master-slave device that responds in a very predictable fashion to simultaneous input pulses; it simply toggles each time the clock pulse coincides with the data pulses (complementary inputs).

The logic elements and connections comprising a J-K flip-flop are in Fig. 5. Two three-input and one one-input NANDs, 3N1, 3N2 and 1N1, together with two two-input NANDs, 2N1 and 2N2, form the "master" flip-flop element. Two more two-input and two three-input NANDs form the "slave" flip-flop element (2N3, 2N4, 3N3 and 3N4). Slave output is cross-coupled back into the master input for combining with J and K inputs and clock pulses.

Flip-flop can be started at zero independent of input - RF Cafe

Fig. 4 - By using 3-input NANDs in place of the NANDs in Fig.  3, flip-flop can be started at zero independent of input.

Functional logic diagram of the J-K flip-flop - RF Cafe

Fig. 5- Functional logic diagram of the J-K flip-flop. Additional flip-flop (see Fig. 4) prevents simultaneous input "racing."

Internal quiescent levels of all individual logic elements are shown by the lower-case letters next to each element terminal. Remember, a bar above a letter signifies that the designated terminal is at the logic ZERO level, and letters without the bar indicate logic ONE level at the designated terminal. The flip-flop operates in the following manner.

Assume dc reset has placed Q low, Q high, and the clock pulse (train) has just gone high and J is high. The dc conditions within the circuit package are indicated by the various lower-case letters at this moment in time.

As the clock pulse falls to ZERO, 3N1-d goes high, adding to 2N1's input. 2N1-c starts to go low, but the stored charge in D1 holds 2N1-c high just long enough that the ONE coming from 1N1-b can add at 2N3's input, subsequently setting 2N3-c low to shift 3N3-a high. By now D1 has discharged and 2N2-a can go low with 2N1-c to complete the toggling of the master flip-flop (2N2-c high). At this moment, the clock pulse has again gone high and 1N1-b has already gone low, and 2N4-c remains high so as to not interfere with the other ONEs at 3N4's inputs.

Earlier, the Q-output, ZERO-level feedback to 3N2-c changed to a ONE level, making the K input ready to accept a data-ONE level (whether one is forthcoming is immaterial at the moment). The Q-output, ONE-level feedback to 3N1-a when Q goes to ZERO cancels the effect of the J ONE level.

This means that only a ONE level at the K input will reset the flip-flop to its former state. Should the J-input level stay at ONE as the K level shifts to ONE, the flip-flop will toggle as just stated. If both J and K levels remain at ONE, the flip-flop will toggle again on the next negative-going clock-pulse edge, and will continue toggling as long as both inputs are high. If the J, K and clock inputs are tied to B+ and the dc set and reset terminals are used, the flip-flop works as an RS flip-flop.

* Publication engineer, Bryant Computer Products.

 

 

Posted May 16, 2019

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