Module 12—Modulation Principles
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AI-1 to AI-6, Index-1 to 2, Assignment 1 , 2
must be constructed so that its output amplitude will vary linearly according to the instantaneous frequency of
the incoming signal. Several types of fm detectors have been developed and are in use, but in this section you
will study three of the most common: (1) the phase-shift detector, (2) the ratio detector, and (3) the gated-beam
To be able to understand the principles of operation
for fm detectors, you need to first study the simplest form of frequency-modulation detector, the SLOPE DETECTOR.
The slope detector is essentially a tank circuit which is tuned to a frequency either slightly above or below the
fm carrier frequency. View (A) of figure 3-9 is a plot of voltage versus frequency for a tank circuit. The
resonant frequency of the tank is the frequency at point 4. Components are selected so that the resonant frequency
is higher than the frequency of the fm carrier signal at point 2. The entire frequency deviation for the fm signal
falls on the lower slope of the bandpass curve between points 1 and 3. As the fm signal is applied to the tank
circuit in view (B), the output amplitude of the signal varies as its frequency swings closer to, or further from,
the resonant frequency of the tank. Frequency variations will still be present in this waveform, but it will also
develop amplitude variations, as shown in view (B). This is because of the response of the tank circuit as it
varies with the input frequency. This signal is then applied to the diode detector in view (C) and the detected
waveform is the output. This circuit has the major disadvantage that any amplitude variations in the RF waveform
will pass through the tank circuit and be detected. This disadvantage can be eliminated by placing a limiter
circuit before the tank input. (Limiter circuits were discussed in NEETS, Module 9, Introduction to
Wave-Generation and Wave-Shaping Circuits.) This circuit is basically the same as an AM detector with the tank
tuned to a higher or lower frequency than the received carrier.
Figure 3-9A.—Slope detector. VOLTAGE VERSUS FREQUENCY PLOT.
Figure 3-9B.—Slope detector. TANK CIRCUIT.
Figure 3-9C.—Slope detector. DIODE DETECTOR.
Q-21. What is the simplest form of fm detector?
Q-22. What is the function of an fm detector?
The FOSTER-SEELEY DISCRIMINATOR is also known as the
PHASE-SHIFT DISCRIMINATOR. It uses a double-tuned RF transformer to convert frequency variations in the received
fm signal to amplitude variations. These amplitude variations are then rectified and filtered to provide a dc
output voltage. This voltage varies in both amplitude and polarity as the input signal varies in frequency. A
typical discriminator response curve is shown in figure 3-10. The output voltage is 0 when the input frequency is
equal to the carrier frequency (FR). When the input frequency rises above the center frequency, the output
increases in the positive direction. When the input frequency drops below the center frequency, the output
increases in the negative direction.
Figure 3-10.—Discriminator response curve.
The output of the Foster-Seeley discriminator is affected not only by the input frequency, but also to a
certain extent by the input amplitude. Therefore, using limiter stages before the detector is necessary.
Circuit Operation of a Foster-Seeley Discriminator
View (A) of figure 3-11 shows a
typical Foster-Seeley discriminator. The collector circuit of the preceding limiter/amplifier circuit (Q1) is
shown. The limiter/amplifier circuit is a special amplifier circuit which limits the amplitude of the signal. This
limiting keeps interfering noise low by removing
excessive amplitude variations from signals. The collector circuit tank consists of C1 and L1. C2 and
L2 form the secondary tank circuit. Both tank circuits are tuned to the center frequency of the incoming fm
signal. Choke L3 is the dc return path for diode rectifiers CR1 and CR2. R1 and R2 are not always necessary but
are usually used when the back (reverse bias) resistance of the two diodes is different. Resistors R3 and R4 are
the load resistors and are bypassed by C3 and C4 to remove rf. C5 is the output coupling capacitor.
Figure 3-11.—Foster-Seeley discriminator. FOSTER-SEELEY DISCRIMINATOR.
CIRCUIT OPERATION AT RESONANCE.—The operation of the Foster-Seeley discriminator can best be explained
using vector diagrams [figure 3-11, view (B)] that show phase relationships between the voltages and currents in
the circuit. Let's look at the phase relationships when the input frequency is equal to the center frequency of
the resonant tank circuit.
The input signal applied to the primary tank circuit is shown as vector Ep. Since coupling capacitor C8 has
negligible reactance at the input frequency, RF choke L3 is effectively in parallel with the primary tank circuit.
Also, because L3 is effectively in parallel with the primary tank circuit, input voltage Ep also appears across
L3. With voltage Ep applied to the primary of T1, a voltage is induced in the secondary which causes current to
flow in the secondary tank circuit. When the input frequency is equal to the center frequency, the tank is at
resonance and acts resistive. Current and voltage are in phase in a resistance circuit, as shown by is and Ep. The
current flowing in the tank causes voltage drops across each half of the balanced secondary winding of transformer
T1. These voltage drops are of equal amplitude and opposite
polarity with respect to the center tap of the winding. Because the winding is inductive, the voltage
across it is 90 degrees out of phase with the current through it. Because of the center-tap arrangement, the
voltages at each end of the secondary winding of T1 are 180 degrees out of phase and are shown as e1 and e2 on the
The voltage applied to the anode of CR1 is the vector sum of voltages Ep and e1, shown as e 3 on the
diagram. Likewise, the voltage applied to the anode of CR2 is the vector sum of voltages Ep and e 2, shown as e4
on the diagram. At resonance e3 and e4 are equal, as shown by vectors of the same length. Equal anode voltages on
diodes CR1 and CR2 produce equal currents and, with equal load resistors, equal and opposite voltages will be
developed across R3 and R4. The output is taken across R3 and R4 and will be 0 at resonance since these voltages
are equal and of appositive polarity. The diodes conduct on opposite half cycles of the input waveform and produce
a series of dc pulses at the RF rate. This RF ripple is filtered out by capacitors C3 and C4.
OPERATION ABOVE RESONANCE.—A phase shift occurs when an input frequency higher than the center frequency
is applied to the discriminator circuit and the current and voltage phase relationships change. When a
series-tuned circuit operates at a frequency above resonance, the inductive reactance of the coil increases and
the capacitive reactance of the capacitor decreases. Above resonance the tank circuit acts like an inductor.
Secondary current lags the primary tank voltage, ep. Notice that secondary voltages e 1 and e2 are still 180
degrees out of phase with the current (iS) that produces them. The change to a lagging secondary current rotates
the vectors in a clockwise direction. This causes el to become more in phase with Ep while e2 is shifted further
out of phase with ep. The vector sum of Ep and e2 is less than that of Ep and e1. Above the center frequency,
diode CR1 conducts more than diode CR2. Because of this heavier conduction, the voltage developed across R3 is
greater than the voltage developed across R4; the output voltage is positive.
OPERATION BELOW RESONANCE.—When the input frequency is lower than the center frequency,
the current and voltage phase relationships change. When the tuned circuit is operated at a frequency lower than
resonance, the capacitive reactance increases and the inductive reactance decreases. Below resonance the tank acts
like a capacitor and the secondary current leads primary tank voltage ep. This change to a leading secondary
current rotates the vectors in a counterclockwise direction. From the vector diagram you should see that e2 is
brought nearer in phase with ep, while el is shifted further out of phase with ep. The vector sum of Ep and e2 is
larger than that of e and e1. Diode CR2 conducts more than diode CR1 below the center frequency. The voltage drop
across R4 is larger than that across R3 and the output across both is negative.
These voltage outputs can be plotted to show the response curve of the discriminator discussed earlier (figure
3-10). When weak AM signals (too small in amplitude to reach the circuit limiting level) pass through the limiter
stages, they can appear in the output. These unwanted amplitude variations will cause primary voltage Ep [view (A)
of figure 3-11] to fluctuate with the modulation and to induce a similar voltage in the secondary of T1. Since the
diodes are connected as half-wave rectifiers, these small AM signals will be detected as they would be in a diode
detector and will appear in the output. This unwanted AM interference is cancelled out in the ratio detector (to
be studied next in this chapter) and is the main disadvantage of the Foster-Seeley circuit.
type of tank circuit is used in the Foster-Seeley discriminator?
Q-24. What is the purpose of CR1 and CR2 in the Foster-Seeley discriminator?
Q-25. What type
of impedance does the tank circuit have above resonance?
The RATIO DETECTOR uses a double-tuned transformer to convert the
instantaneous frequency variations of the fm input signal to instantaneous amplitude variations. These amplitude
variations are then rectified to provide a dc output voltage which varies in amplitude and polarity with the input
signal frequency. This detector demodulates fm signals and suppresses amplitude noise without the need of limiter
Figure 3-12 shows a typical ratio detector. The input tank capacitor (C1)
and the primary of transformer T1 (L1) are tuned to the center frequency of the fm signal to be demodulated. The
secondary winding of T1 (L2) and capacitor C2 also form a tank circuit tuned to the center frequency. Tertiary
(third) winding L3 provides additional inductive coupling which reduces the loading effect of the secondary on the
primary circuit. Diodes CR1 and CR2 rectify the signal from the secondary tank. Capacitor C5 and resistors R1 and
R2 set the operating level of the detector. Capacitors C3 and C4 determine the amplitude and polarity of the
output. Resistor R3 limits the peak diode current and furnishes a dc return path for the rectified signal. The
output of the detector is taken from the common connection between C3 and C4. Resistor RL is the load resistor.
R5, C6, and C7 form a low-pass filter to the output.
Figure 3-12.—Ratio detector.
This circuit operates on the same principles of phase shifting as did the Foster-Seeley discriminator.
In that discussion, vector diagrams were used to illustrate the voltage amplitudes and polarities for conditions
at resonance, above resonance, and below resonance. The same vector diagrams apply to the ratio detector but will
not be discussed here. Instead, you will study the resulting current flows and polarities on simplified schematic
diagrams of the detector circuit.
OPERATION AT RESONANCE.—When the input voltage Ep is
applied to the primary in figure 3-12 it also appears across L3 because, by inductive coupling, it is effectively
connected in parallel with the primary tank circuit. At the same time, a voltage is induced in the secondary
winding and causes current to flow around the secondary tank circuit. At resonance the tank acts like a resistive
circuit; that is,
the tank current is in phase with the primary voltage Ep. The current flowing in the tank circuit
causes voltages e1 and e2 to be developed in the secondary winding of T1. These voltages are of equal magnitude
and of opposite polarity with respect to the center tap of the winding. Since the winding is inductive, the
voltage drop across it is 90 degrees out of phase with the current through it.
Figure 3-13 is a simplified
schematic diagram of a ratio detector at resonance. The voltage applied to the cathode of CR1 is the vector sum of
e1 and Ep. Likewise, the voltage applied to the anode of CR2 is the vector sum of e2 and Ep. No phase shift occurs
at resonance and both voltages are equal. Both diodes conduct equally. This equal current flow causes the same
voltage drop across both R1 and R2. C3 and C4 will charge to equal voltages with opposite polarities. Let’s assume
that the voltages across C3 and C4 are equal in amplitude (5 volts) and of opposite polarity and the total charge
across C5 is 10 volts. R1 and R2 will each have 5 volts dropped across them because they are of equal values. The
output is taken between points A and B. To find the output voltage, you algebraically add the voltages between
points A and B (loop ACB or ADB). Point A to point D is 5 volts. Point D to point B is + 5 volts. Their algebraic
sum is 0 volts and the output voltage is 0 at resonance. If the voltages on branch ACB were figured, the same
output would be found because the circuit branches are in parallel.
Figure 3-13.—Current flow and polarities at resonance.
When the input signal reverses polarity, the secondary voltage across L2 also reverses. The diodes will
be reverse biased and no current will flow. Meanwhile, C5 retains most of its charge because of the long time
constant offered in combination with R1 and R2. This slow discharge helps to maintain the output.
OPERATION ABOVE RESONANCE.—When a tuned circuit (figure 3-14) operates at a frequency higher than
resonance, the tank is inductive. The secondary current i lags the primary voltage ep. Secondary voltage e1 is
nearer in phase with primary voltage e, while e2 is shifted further out of phase with ep. The vector sum of e1 and
Ep is larger than that of e2 and Ep. Therefore, the voltage applied to the cathode of CR1 is greater than the
voltage applied to the anode of CR2 above resonance.
Figure 3-14.—Current flow and polarities above resonance.
Assume that the voltages developed above resonance are such that the higher voltage on the cathode of
CR1 causes C3 to charge to 8 volts. The lower voltage on the anode of CR2 causes C4 to charge to 2 volts.
Capacitor C5 remains charged to the sum of these two voltages, 10 volts. Again, by adding the voltages in loop ACB
or ADB between points A and B, you can find the output voltage. Point A to point D equals -2 volts. Point D to
point B equals +5 volts. Their algebraic sum, and the output, equals +3 volts when tuned above resonance. During
the negative half cycle of the input signal, the diodes are reverse biased and C5 helps maintain a constant
OPERATION BELOW RESONANCE.—When a tuned circuit operates below resonance (figure
3-15), it is capacitive. Secondary current is leads the primary voltage Ep and secondary voltage e2 is nearer in
phase with primary voltage ep. The vector sum of e2 and Ep is larger than the sum of e1 and ep. The voltage
applied to the anode of CR2 becomes greater than the voltage applied to the cathode of CR1 below resonance.
Figure 3-15.—Current flow and polarities below resonance.
Assume that the voltages developed below resonance are such that the higher voltage on the anode of CR2
causes C4 to charge to 8 volts. The lower voltage on the cathode of CR1 causes C3 to charge to 2 volts. Capacitor
C5 remains charged to the sum of these two voltages, 10 volts. The output voltage equals -8 volts plus +5 volts,
or -3 volts, when tuned below resonance. During the negative half cycle of the input signal, the diodes are
reverse biased and C5 helps maintain a constant output.
Advantage of a Ratio Detector
The ratio detector is not affected by amplitude variations on the fm wave. The output of the detector adjusts
itself automatically to the average amplitude of the input signal. C5 charges to the sum of the voltages across R1
and R2 and, because of its time constant, tends to filter out any noise impulses. Before C5 can charge or
discharge to the higher or lower potential, the noise disappears. The difference in charge across C5 is so slight
that it is not discernible in the output. Ratio detectors can operate with as little as 100 millivolts of input.
This is much lower than that required for limiter saturation and less gain is required from preceding stages.
Q-26. What is the primary advantage of a ratio detector?
Q-27. What is the purpose of C5 in figure
An fm demodulator employing a completely
different detection principle is the GATED-BEAM DETECTOR (sometimes referred to as the QUADRATURE DETECTOR). A
simplified diagram of a
gated-beam detector is shown in figure 3-16. It uses a gated-beam tube to limit, detect, and amplify
the received fm signal. The output voltage is 0 when the input frequency is equal to the center frequency. When
the input frequency rises above the center frequency, the output voltage goes positive. When the input frequency
drops below the center frequency, the output voltage goes negative.
Figure 3-16.—Gated-beam detector.
The gated-beam detector employs a specially designed gated-beam
tube. The elements of this tube are shown in figure 3-17. The focus electrode forms a shield around the tube
cathode except for a narrow slot through which the electron beam flows. The beam of electrons flows toward the
limiter grid which acts like a gate. When the gate is open, the electron beam flows through to the next grid. When
closed, the gate completely stops the beam.
Figure 3-17.—Gated-beam tube physical layout.
After the electron beam passes the limiter grid, the screen grid refocuses the beam toward the
quadrature grid. The quadrature grid acts much the same as the limiter grid; it either opens or closes the passage
for electrons. These two grids act similar to an AND gate in digital devices; both gates must be open for the
passage of electrons to the plate. Either grid can cut off plate current. AND gates were presented in NEETS,
Module 13, Introduction to Number Systems, Boolean Algebra, and Logic Circuits.
Look again at the circuit
in figure 3-16. With no signal applied to the limiter grid (3), the tube conducts. The electron beam moving near
the quadrature grid (5) induces a current into the grid which develops a voltage across the high-Q tank circuit
(L3 and C3). C3 charges until it becomes sufficiently
negative to cut off the current flow. L3 tends to keep the current moving and, as its field collapses,
discharges C3. When C3 discharges sufficiently, the quadrature grid becomes positive, grid current flows, and the
cycle repeats itself. This tank circuit (L3 and C3) is tuned to the center frequency of the received fm signal so
that it will oscillate at that frequency.
The waveforms for the circuit are shown in figure 3-18. View (A)
is the fm input signal. The limiter-grid gate action creates a wave shape like view (B) because the tube is either
cut off or saturated very quickly by the input wave. Note that this is a square wave and is the current waveform
passing the limiter grid.
Figure 3-18A.—Gated-beam detector waveforms.
Figure 3-18B.—Gated-beam detector waveforms.
At the quadrature grid the voltage across C3 lags the current which produces it [view (C)]. The result
is a series of pulses, shown in view (D), appearing on the quadrature grid at the center frequency, but lagging
the limiter-grid voltage by 90 degrees. Because the quadrature grid has the same conduction and cutoff levels as
the limiter grid, the resultant current waveform will be transformed into a square wave.
Figure 3-18C.—Gated-beam detector waveforms.
Figure 3-18D.—Gated-beam detector waveforms.
Both the limiter and quadrature grids must be positive at the same time to have plate current. You can see how
much conduction time occurs for each cycle of the input by overlaying the current waveforms in views (B) and (D),
as shown in view (E). The times when both grids are positive are shown by the shaded area of view (E). These plate
current pulses are shown for operation at resonance in view (F).
Figure 3-18E.—Gated-beam detector waveforms.
Figure 3-18F.—Gated-beam detector waveforms.
Now consider what happens with a deviation in frequency at the input. If the frequency increases, the
frequency across the quadrature tank also increases. Above resonance, the tank appears capacitive to the induced
current; voltage then lags the applied voltage by more than 90 degrees, as shown in view (G). Note in view (H)
that the two grid signals have moved more out of phase and the average plate current level has decreased.
Figure 3-18G.—Gated-beam detector waveforms.
Figure 3-18H.—Gated-beam detector waveforms.
As the input frequency decreases, the opposite action takes place. The two grid signals move more in
phase, as shown in view (I), and the average plate current increases, as shown in view (J).
Figure 3-18I.—Gated-beam detector waveforms.
Figure 3-18J.—Gated-beam detector waveforms.
View (K) shows the resultant plate-current pulses when an fm signal is applied to a gated-beam detector. Plate
load resistor R4 and capacitor C6 form an integrating network which filters these pulses to form the sine-wave
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