|Achieving Design Security Requirements Using
eASIC’s Technology | easic.com/pdf/WP_0004.pdf
White Paper from eASIC Corp.
The Art of Successful ASIC Design | opencores.org/articles.cgi/view/10
From Opencores.org by John Bedford Solomon.
ASIC Basics Tutorial |
An overview or tutorial of the basics of the ASIC, its advantages and
disadvantages and a tutorial about the ASIC design process and the use of an ASIC design service. From
ASIC Design at Home
From Journal of Universal Computer Science, Heinrichmeyer Friedrich.
ASIC Design Channel
ASIC design articles, product information and vendors from Power Design 365.
ASIC Design Guidelines | atmel.com/dyn/resources/prod_documents/doc1205.pdf
Application note from Atmel Corporation.
ASIC Design Tips
A mix of useful tips from Doulos Ltd.
ASIC Design Methodology Primer
Abstract from IBM.
ASIC-Style Design Techniques for Programmable Devices |
By Salil Raje Hier Design.
ASIC to FPGA Design Methodology &
Guidelines | altera.com/literature/an/an311.pdf
From Altera Corporation.
ASIC Volume Production Without Breaking the Bank | chipx.com/images/stories/pdf/asic_volume_wp-0404.pdf
Whitepaper from ChipX,
Creating a Timing Constraint File for RTL Synthesis Using the Synplify ASIC® Tool
Application note from Synplicity, Inc.
Design Guidelines for Optimal Results in FPGAs | altera.com/literature/cp/fpgas-optimal-results-396.pdf
By Jennifer Stephenson, Altera Corporation.
Design your own ASIC | ap.pennnet.com/Articles/Article_Display.cfm?Section=Articles&Subsection=Display&ARTICLE_ID=185763
From Advanced Packaging, by By Donald Hawk and Kevin Kolwicz.
Embedding the 1-Wire Master |
Application note from Maxim Integrated Products.
Mixed Signal ASIC Design Methodology for Space Applications |
By L. Foglia.
Mixed-Signal ASIC Success Story | chipx.com/images/stories/pdf/mixed-signal_asic_successstory.pdf
Whitepaper from ChipX, Inc.
Navigating the Silicon Jungle: FPGA or ASIC? | chipdesignmag.com/display.php?articleId=115&issueId=11
From Chip Design, by John Blyler.
SideChip ASIC Approach Increases Chip Designers' Flexibility |
Whitepaper from ChipX, Inc.
SOI Eases Radiation-Hardened ASIC Designs | eetimes.com/news/design/showArticle.jhtml?articleID=165700727&printable=true
From EE Times, by Thomas Romanko and Brian Clegg.
Translation Of Existing ASIC Designs | eetasia.com/ARTICLES/2000AUG/2000AUG31_ICD_AN.PDF
Tutorial 1 - Introduction to ASIC Design Methodology | ece.ncsu.edu/asic/tutorials/tutor1/tutor1.pdf
This tutorial is meant only to provide the reader
with a brief introduction to those portions of the design process that occur in the HDL Design Capture and
HDL Design Synthesis phases, and a brief overview of the design automation tools typically used for these
portions of the design process.