Analog Devices Clocking ICs Improve Performance in Timing Signal Chain for Communications Infrastructure
• AD9553 clock generator features pin-programming and customizable SPI programming modes to facilitate
designs of GPON, OC-48 optical network and wireless communications infrastructure equipment.
high-speed clock fanout buffer lowers jitter performance in SONET and wireless base station systems.
Mass.--(BUSINESS WIRE)-- Analog Devices, Inc. (ADI), a global leader in high-performance semiconductors for
signal-processing applications and leading provider of data conversion technology, today introduced two clock
products that, when designed in as part of a complete timing signal chain, improve performance and reduce
programming and design complexity in synchronous optical networks and wireless base stations.
AD9553 clock generator is recommended for low-cost clock translation needs in GPON, SONET/SDH OC-48
(synchronous optical networking/synchronous digital hierarchy), test and measurement, data acquisition, Ethernet,
Fibre Channel, T1/E1, broadcast video and other wireless and wired communications applications.
ADCLK944 is designed to improve SNR (signal-to-noise ratio) performance from data converters in wireless base
stations as well as provide low-power, low-jitter performance for SONET/SDH optical networks. More designers turn
to ADI than any other supplier for the high-performance data converters and clocking technology required to bridge
the analog and digital worlds in today’s electronic systems. AD9553 Clock Generator Reduces Programming Time
The AD9553 clock generator, available at about half the cost of competing solutions, features pre-set
input/output frequency ratios that can be easily pin-programmed. The pin-programming mode provides a matrix of
standard input/output frequency translations, while a SPI (serial peripheral interface) port is available to
program customized input-to-output frequency translations. The AD9553 clock generator features both jitter
clean-up and clock translation. The variety of input/output clock frequency combinations and its output stage
flexibility eliminate up to two discrete PLLs (phase-locked loops) and various other discrete components, reducing
board space, design complexity and simplifying programming.
The AD9553 features a holdover mode that
provides output signals even in the absence of a reference input. If one of the CMOS references fails, the clock
generator also includes a switchover function that provides additional security without losing the lock on
ADCLK944 Clock Buffer Provides Low-Jitter Performance The ADCLK944 clock fanout
buffer features the industry’s lowest jitter figure of 50-fs (femto seconds) for communications equipment that
require multiple high-performance clock signals without compromising high-speed signal conversion in LTE, MC-GSM
and other wireless network applications. This jitter performance, combined with low power consumption per channel,
also make the ADCLK944 effective for applications based on the Gigabit Ethernet (GbE) and SONET/SDH optical
network multiplexing protocols. The increasing data rates in SONET/SDH and GbE systems necessitate clocks with
very low jitter. The ADCLK944’s ultra-low jitter contributes very little to the system jitter budget thus allowing
maximum design flexibility for the SerDes (serializer/deserializer) clock designer. Low power is also important
because today's systems use high density SONET boards containing multiple channels.
The ADCLK944 clock
fanout buffer provides four LVPECL outputs that operate at speeds up to 7 GHz while achieving broadband random rms
(root-mean square) additive jitter of 50 fs. The ADCLK944 clock fanout buffer’s extremely low jitter and max
output-to-output skew of 15 ps (pico seconds) are designed for wired and wireless equipment that requires clean
clock signals for high-speed converter clocking, such as LTE and multi-carrier GSM communications base stations.
The jitter performance also contributes to addressing clocking-distribution jitter generation requirements for
high-speed OC-192 and OC-768 SONET line cards.
The buffer’s low-noise performance enables significantly
higher SNR levels, particularly when designed in as part of a complete signal chain incorporating DACs
(digital-to-analog converters), ADCs (analog-to-digital converters) and clock generators.
As part of an
optimized communications signal chain, the ADCLK944 clock buffer is designed to operate with ADI’s AD9779 Dual
16-Bit, 1 GSPS DAC; AD9739 14-Bit, 2500 MSPS, RF DAC and AD9789 14-Bit, 2400 MSPS TxDAC+ with 4-Channel Signal
Processing and ADCs such as the AD9445 14-Bit, 105 MSPS / 125 MSPS and AD9446 16-Bit, 80 MSPS / 100 MSPS.
Availability and Pricing Product Sample
Availability Temperature Range Price Each Per 1,000 Packaging
AD9553 NOW -40°C to +85°C $5.10 5 mm x 5 mm 32-lead LFCSP ADCLK944
NOW -40°C to +85°C $6.00 3 mm x3 mm 16-lead LFCSP
Innovation, performance, and excellence are
the cultural pillars on which Analog Devices has built one of the longest-standing, highest-growth companies
within the technology sector. Acknowledged industry-wide as the world leader in data-conversion and
signal-conditioning technologies, Analog Devices serves over 60,000 customers, representing virtually all types of
electronic equipment. Celebrating over 40 years as a leading global manufacturer of high-performance integrated
circuits for analog- and digital-signal processing applications, Analog Devices is headquartered in Norwood,
Massachusetts, with design and manufacturing facilities throughout the world. Analog Devices' common stock is
listed on the New York Stock Exchange under the ticker “ADI” and is included in the S&P 500 Index.