Ph: 408-306-3666, Email:
400 Riverside Ct, Apt #310, Santa
Seeking a challenging full time position in RFIC Analog
Design in a fast paced environment.
with specialization in RFIC and Analog IC Design
4+ years experience in the field of RFIC, MMIC and
Experience in design of Power Amplifiers, LNA’s , Mixers for WLAN and WiMAX
applications on CMOS
Design and testing experience for CATV products used in RFOG setup
multilayer PCB RF boards, testing and troubleshooting of RF/ Microwave modules and MMIC’s
with Cadence and other EDA tools and adept at MATLAB programming
Excellent communication and
Inc./CTDI Livermore,CA [RF Engineer] Mar’09 - Present
• Managed CATV Transceiver design,
development and test for RFOG market
• Characterization, test, debug of Return receivers,
transmitters and transceivers
• BER and packet loss test bench setup
• Characterizing new
components like BIDI’s, Amplifiers, Diplexers, Switches used in RFOG products
• Product documentation
Excelics Seminconductor,Sunnyvale ,CA [RFIC Design Engineer] Aug’08 – Feb’09
• RF Pin attenuator design and layout for frequency bands in 1-32 GHz
• Lange coupler EM simulation,
layout and tile planning for frequencies upto 32 GHz
• Broadband Power Detector Module design and
test, delivered to the customer
• Participate and give design reviews
SM Wireless Solutions
Pvt. Ltd., Nagpur, India [Sr. RFIC Design Engineer] Jun’05 – Dec’06
• Project lead for inhouse and
• Power Amplifier design, layout for 802.11a/b/g and 3.5 GHz band on CMOS and GaAs
• Broadband and Narrowband LNA for 802.11a/b/g,MMDS and WiMAX Bands
• Cable TV Amplifier Chip design
• Gilbert Cell Mixer design and layout
• PDK verification of 0.18 um CMOS
Troubleshoot MMIC die, packaged chips using PNA, Spectrum Analyzer
• Tile Planning and Tape Out
Train junior designers on the RF Design Tools and basics of RFIC/MMIC Design
RF Arrays Systems
Pvt. Ltd., Nagpur, India [Jr. RFIC Design Engineer] Aug’04 – May’05
• WLAN Front End Module design,
2.4 GHz-2.5 GHz, on Genesys Eagleware
which was fabricated and tested
• Design and layout HPF on
ADS using Momentum for EM simulation
• Simulation of MMIC PA for 802.11a WLAN band on GaAs pHEMT in
ADS and AWR
EDA TOOLS USED
• CADENCE Spectre,
• Agilent’s ADS, AWR’s Microwave Office,
• AUTOCAD, Solidworks,Genesys
Eagleware , MATLAB, Mentor Graphics
Analog IC Design of OTA, voltage references, active filter
• MMIC, RF Module Design, Testing and
• Proficient at using PNA, Scalar Network Analyzers, Spectrum Analyzers
Board Design and Test Fixture Design for RF chip testing
Masters in Electrical Engineering, GPA 3.789
State University, San Jose, CA Dec’08
CMOS RFIC Design , Analog IC Design, Mixed Signal IC Design, Linear Systems, Semiconductor Device
Physics, VLSI Technologies, Probabilty of Random Variables and Stochastic Processes.
NOISE PARAMETER EXTRACTION OF NANOWIRE TRANSISTORS Dec’08
Masters Thesis which involved noise parameter modeling of nanowire transistors.
It included devicing
new equations for the noise parameters and verifying them with simulated data.
DIGITAL PLL DESIGN
This was a final project for Mixed Signal IC design course. It involved design of VCO,
Phase Frequency Detector,Charge pump, Loop Filter and Divide by2 in IBM .13um CMOS
operating frequency of 1GHz. Design was completed using Cadence Spectre EDA.
OTA DESIGN Dec’07
Design of an OTA (Folded Cascode Topology) on 0.25um TSMC foundry using Cadence.
GBW product was
250MHz for unity gain at 5pF loading with a phase margin of 62o .
Simulated gain was 86 dB.
PHASE LOCKED LOOP ANALYSIS May’07
To derive and analyze the transfer funtion of the PLL for various
the Loop filter and plot the frequency response,Step response of the system using
CMOS RFIC DESIGN – TECHNOLOGY OVERVIEW May’07
This report was a comprehensive study of
evolution of 900MHz RFIC systems, the impact
of scaling on MOS transistors, limitations in
scaling,various MMIC fabrication technologies,
their comparison with CMOS and the layout issues in
100 GHz,0.5V RFIC design.
EVOLUTION OF TRI-GATE FET May’07
The report stated the evolution of
Tri-gate FET,recent breakthroughs in 3-D architechture
of FET’s ,its advantages and implementation
in future IC’s.
MATLAB workshop, San Jose State University. Oct’07, Apr’08, Oct’08
The workshop covered Introduction
to MATLAB programming and Simulink overview for an audience of around 40.
Guest Speaker at RF
Design Seminar conducted at VNIT , Nagpur. Jan’08
Presentation on “ RF Amplifier Design and Layout
Introduction to RF Power Amplifer and LNA Design and layout intricacies at high
Awarded Louie Barozzi scholarship on 17th April’ 2008 for academic excellence in
Graduate Program as an International Student and contribution to community service.