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Resume submission - Deshmukh - RF Cafe Forums

Because of the high maintenance needed to monitor and filter spammers from the RF Cafe Forums, I decided that it would be best to just archive the pages to make all the good information posted in the past available for review. It is unfortunate that the scumbags of the world ruin an otherwise useful venue for people wanting to exchanged useful ideas and views. It seems that the more formal social media like Facebook pretty much dominate this kind of venue anymore anyway, so if you would like to post something on RF Cafe's Facebook page, please do.

Below are all of the forum threads, including all the responses to the original posts.

 Post subject: Resume submission
Posted: Thu Aug 19, 2010 2:50 am 

Joined: Sat Feb 21, 2009 6:46 pm
Posts: 1
Location: Santa Clara,CA
Pallavi Deshmukh
Ph: 408-306-3666, Email: pallavi.rf@gmail.com
400 Riverside Ct, Apt #310, Santa Clara,CA 95054

Seeking a challenging full time position in RFIC Analog Design in a fast paced environment.

MSEE with specialization in RFIC and Analog IC Design
4+ years experience in the field of RFIC, MMIC and Microwave design
Experience in design of Power Amplifiers, LNA’s , Mixers for WLAN and WiMAX applications on CMOS
Design and testing experience for CATV products used in RFOG setup
Worked on multilayer PCB RF boards, testing and troubleshooting of RF/ Microwave modules and MMIC’s
Proficient with Cadence and other EDA tools and adept at MATLAB programming
Excellent communication and presentation skills

Alloptic Inc./CTDI Livermore,CA [RF Engineer] Mar’09 - Present

• Managed CATV Transceiver design, development and test for RFOG market
• Characterization, test, debug of Return receivers, transmitters and transceivers
• BER and packet loss test bench setup
• Characterizing new components like BIDI’s, Amplifiers, Diplexers, Switches used in RFOG products
• Product documentation and organization

Excelics Seminconductor,Sunnyvale ,CA [RFIC Design Engineer] Aug’08 – Feb’09
• RF Pin attenuator design and layout for frequency bands in 1-32 GHz
• Lange coupler EM simulation, layout and tile planning for frequencies upto 32 GHz
• Broadband Power Detector Module design and test, delivered to the customer
• Participate and give design reviews

SM Wireless Solutions Pvt. Ltd., Nagpur, India [Sr. RFIC Design Engineer] Jun’05 – Dec’06
• Project lead for inhouse and customer projects
• Power Amplifier design, layout for 802.11a/b/g and 3.5 GHz band on CMOS and GaAs
• Broadband and Narrowband LNA for 802.11a/b/g,MMDS and WiMAX Bands
• Cable TV Amplifier Chip design and test
• Gilbert Cell Mixer design and layout
• PDK verification of 0.18 um CMOS
• Test, Troubleshoot MMIC die, packaged chips using PNA, Spectrum Analyzer
• Tile Planning and Tape Out
• Train junior designers on the RF Design Tools and basics of RFIC/MMIC Design

RF Arrays Systems Pvt. Ltd., Nagpur, India [Jr. RFIC Design Engineer] Aug’04 – May’05
• WLAN Front End Module design, 2.4 GHz-2.5 GHz, on Genesys Eagleware
which was fabricated and tested
• Design and layout HPF on ADS using Momentum for EM simulation
• Simulation of MMIC PA for 802.11a WLAN band on GaAs pHEMT in ADS and AWR

• CADENCE Spectre, SpectreRF, Virtuoso
• Agilent’s ADS, AWR’s Microwave Office,
• AUTOCAD, Solidworks,Genesys Eagleware , MATLAB, Mentor Graphics

• Analog IC Design of OTA, voltage references, active filter
• MMIC, RF Module Design, Testing and Troubleshooting
• Proficient at using PNA, Scalar Network Analyzers, Spectrum Analyzers
• PCB Board Design and Test Fixture Design for RF chip testing

Masters in Electrical Engineering, GPA 3.789
San Jose State University, San Jose, CA Dec’08
CMOS RFIC Design , Analog IC Design, Mixed Signal IC Design, Linear Systems, Semiconductor Device Physics, VLSI Technologies, Probabilty of Random Variables and Stochastic Processes.

Masters Thesis which involved noise parameter modeling of nanowire transistors.
It included devicing new equations for the noise parameters and verifying them with simulated data.

This was a final project for Mixed Signal IC design course. It involved design of VCO,
Phase Frequency Detector,Charge pump, Loop Filter and Divide by2 in IBM .13um CMOS
process. VCO operating frequency of 1GHz. Design was completed using Cadence Spectre EDA.

Design of an OTA (Folded Cascode Topology) on 0.25um TSMC foundry using Cadence.
GBW product was 250MHz for unity gain at 5pF loading with a phase margin of 62o .
Simulated gain was 86 dB.

To derive and analyze the transfer funtion of the PLL for various configurations of
the Loop filter and plot the frequency response,Step response of the system using MATLAB.

This report was a comprehensive study of evolution of 900MHz RFIC systems, the impact
of scaling on MOS transistors, limitations in scaling,various MMIC fabrication technologies,
their comparison with CMOS and the layout issues in 100 GHz,0.5V RFIC design.

The report stated the evolution of Tri-gate FET,recent breakthroughs in 3-D architechture
of FET’s ,its advantages and implementation in future IC’s.

Instructor for MATLAB workshop, San Jose State University. Oct’07, Apr’08, Oct’08
The workshop covered Introduction to MATLAB programming and Simulink overview for an audience of around 40.

Guest Speaker at RF Design Seminar conducted at VNIT , Nagpur. Jan’08
Presentation on “ RF Amplifier Design and Layout Considerations”
Introduction to RF Power Amplifer and LNA Design and layout intricacies at high frequency

Awarded Louie Barozzi scholarship on 17th April’ 2008 for academic excellence in
Graduate Program as an International Student and contribution to community service.

Posted  11/12/2012
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