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syncronization and tracking circuit - RF Cafe Forums

Because of the high maintenance needed to monitor and filter spammers from the RF Cafe Forums, I decided that it would be best to just archive the pages to make all the good information posted in the past available for review. It is unfortunate that the scumbags of the world ruin an otherwise useful venue for people wanting to exchanged useful ideas and views. It seems that the more formal social media like Facebook pretty much dominate this kind of venue anymore anyway, so if you would like to post something on RF Cafe's Facebook page, please do.

Below are all of the forum threads, including all the responses to the original posts.


harry
Post subject: syncronization and tracking circuit Posted: Sat Oct 22, 2005 2:40 am
hi friends,
I want to implement syncronizaion and tracking circuit.could any one please give me detail design? or any links?

I got a few which shows only blocks not actual hardware componenets to build that.i need detailed things,I would be thankful to you .

please do respond positively.

thanks
Harry


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Guest
Post subject: Synch circuitsPosted: Sun Oct 23, 2005 5:20 pm
Harry,

There is a very wide range of possible uses for a synchronizer and/or tracker, ranging from low-speed baseband data at 1200 bits/second up to UltraWideBand. Audio to microwaves: no one circuit will handle it all.

If you want help, you need to ask specific enough questions so that we can help you - otherwise, we would simply be "shooting in the dark", hoping to hit your target.

So:
What frequencies? What data rates? What context? (High SNR, low SNR, etc). Modulation (if any)?

Good Luck!


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Harry
Post subject: Re: Synch circuitsPosted: Sat Nov 05, 2005 4:08 am
Guest wrote:
Harry,

There is a very wide range of possible uses for a synchronizer and/or tracker, ranging from low-speed baseband data at 1200 bits/second up to UltraWideBand. Audio to microwaves: no one circuit will handle it all.

If you want help, you need to ask specific enough questions so that we can help you - otherwise, we would simply be "shooting in the dark", hoping to hit your target.

So:
What frequencies? What data rates? What context? (High SNR, low SNR, etc). Modulation (if any)?

Good Luck!


Hi ,
I do have somespecifications with me now.

frequency of PN CODE is 1 MHz.I will be using BPSK modulation.
data rate is 10 Khz.

the SNR is 5-10 dB.
so i need some circuit description to lock the incoming signal at receiver and then track it.(Acquisition and Synchronization circuit)

I ould really appriciate your help.
Thanks a lot in advance
Harry


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Guest
Post subject: SyncPosted: Sat Nov 05, 2005 4:13 pm
Hi!

Thanks for the information - there's still some fuzziness. Is it:
1. Carrier 1 MHz, Chip Rate 10 kHz, Data Rate lower, or is it
2. Carrier unspecified, Chip Rate 1 MHz, Data Rate 10 kHz?

There are several kinds of synchronization, also - do you need information on
1. Carrier Sync (Costas Loop)
2. Chip Sync (Early/Late or Delay-Locked Loop) or
3. Bit sync (chip correlation)
4. Byte/Word sync (and in that case, is the data asynchronous, like RS-232 serial data with start and stop bits, or is it synchronous, needing a preamble and an occasional SYN character?)

Good Luck!


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Guest
Post subject: Re: SyncPosted: Sat Nov 05, 2005 7:50 pm
Guest wrote:
Hi!

Thanks for the information - there's still some fuzziness. Is it:
1. Carrier 1 MHz, Chip Rate 10 kHz, Data Rate lower, or is it
2. Carrier unspecified, Chip Rate 1 MHz, Data Rate 10 kHz?

There are several kinds of synchronization, also - do you need information on
1. Carrier Sync (Costas Loop)
2. Chip Sync (Early/Late or Delay-Locked Loop) or
3. Bit sync (chip correlation)
4. Byte/Word sync (and in that case, is the data asynchronous, like RS-232 serial data with start and stop bits, or is it synchronous, needing a preamble and an occasional SYN character?)

Good Luck!


Hi ,
Thanks for the reply

Yes that is true PN code frequncy(1MHz) is greater than that of Binary data rate(10 Khz).That is how spectrum is spreaded in DSSS.

I want to lock receiver's PN code (which is delayed verison of the transmitter PN code) with that of transmitter's PN code .
Both the code operates on the same frequency.

Here are the questions that comes in my mind ,but answer of all these are still unknown to me .


How can i generate delay circuit? like receiver code is delayed by 1 bit or so on since both PN code will be using same Clock.

and once i get the delayed PN code at receiver how can i compare both the code?
if i get a match what should be the next step?
how can i correlate that all the bits are matched after the first match is achieved ?
Once i get the initial acquistion phase i need to lock the receiver code to that of transmitter.



Any circuit schematic,document,design ?


I would be thanks full to you if you could let me know how can i implement ?

Thanks for help
Please dont get upset wid me if i do ask some basic question.

Have a gr8 time
Harry.


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HARRY
Post subject: Re: SyncPosted: Sun Nov 06, 2005 2:03 pm
Anonymous wrote:
Guest wrote:
Hi!

Thanks for the information - there's still some fuzziness. Is it:
1. Carrier 1 MHz, Chip Rate 10 kHz, Data Rate lower, or is it
2. Carrier unspecified, Chip Rate 1 MHz, Data Rate 10 kHz?

There are several kinds of synchronization, also - do you need information on
1. Carrier Sync (Costas Loop)
2. Chip Sync (Early/Late or Delay-Locked Loop) or
3. Bit sync (chip correlation)
4. Byte/Word sync (and in that case, is the data asynchronous, like RS-232 serial data with start and stop bits, or is it synchronous, needing a preamble and an occasional SYN character?)

Good Luck!


Hi ,
Thanks for the reply

Yes that is true PN code frequncy(1MHz) is greater than that of Binary data rate(10 Khz).That is how spectrum is spreaded in DSSS.

I want to lock receiver's PN code (which is delayed verison of the transmitter PN code) with that of transmitter's PN code .
Both the code operates on the same frequency.

Here are the questions that comes in my mind ,but answer of all these are still unknown to me .


How can i generate delay circuit? like receiver code is delayed by 1 bit or so on since both PN code will be using same Clock.

and once i get the delayed PN code at receiver how can i compare both the code?
if i get a match what should be the next step?
how can i correlate that all the bits are matched after the first match is achieved ?
Once i get the initial acquistion phase i need to lock the receiver code to that of transmitter.



Any circuit schematic,document,design ?


I would be thanks full to you if you could let me know how can i implement ?

Thanks for help
Please dont get upset wid me if i do ask some basic question.

Have a gr8 time
Harry.


Hi Guest,
I request you to reply my queries.I would appriciate your help
Thanks
Harry.


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Guest
Post subject: SyncPosted: Sun Nov 06, 2005 3:28 pm
Hi Harry,
OK, it's option 2: chip rate 1 MHz, data date 10 kHz, spreading ratio 10.

Assuming that the architecture of the receiver is a double-balanced mixer being driven by the PN despread code before a conventional, low-speed 10 kbps demodulator, then what you need is a "sliding correlator".

The usual reference I give people for this is a somewhat-older book, Spread Spectrum Systems, by Robert Dixon (2nd ed, 1984), pages 218-222.

The basic idea is that the chip frequency at the receiver is slightly offset from the chip frequency of the transmitter (your "1 MHz" clock). This difference in frequencies causes the two sequences to shift with respect to each other (on an oscilloscope, it looks like one waveform is sliding by the other one. At some point, they line up, and the chips disapppear, reducing the bandwidth of the signal. At that point, you switch the frequency of the receiver despread chip clock to exactly that of the transmitter, and keep it in lock with conventional means

Those conventional means include "early-late" techniques. Here, you use 3 double-balanced mixers, one early, one for the real demodulator, and one late, and use those signals to control the VCXO which is your 1 MHz chip clock oscillator.

I hope this helps - if not, ask a more specific question & I'll try to understand what you need.

Good Luck!


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Guest
Post subject: SyncPosted: Sun Nov 06, 2005 3:55 pm
Here's a web reference to correlators, sliding and otherwise:
http://www.sss-mag.com/corr.html

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Harry
Post subject: Re: SyncPosted: Wed Nov 09, 2005 2:54 pm
Guest wrote:
Hi Harry,
OK, it's option 2: chip rate 1 MHz, data date 10 kHz, spreading ratio 10.

Assuming that the architecture of the receiver is a double-balanced mixer being driven by the PN despread code before a conventional, low-speed 10 kbps demodulator, then what you need is a "sliding correlator".

The usual reference I give people for this is a somewhat-older book, Spread Spectrum Systems, by Robert Dixon (2nd ed, 1984), pages 218-222.

The basic idea is that the chip frequency at the receiver is slightly offset from the chip frequency of the transmitter (your "1 MHz" clock). This difference in frequencies causes the two sequences to shift with respect to each other (on an oscilloscope, it looks like one waveform is sliding by the other one. At some point, they line up, and the chips disapppear, reducing the bandwidth of the signal. At that point, you switch the frequency of the receiver despread chip clock to exactly that of the transmitter, and keep it in lock with conventional means

Those conventional means include "early-late" techniques. Here, you use 3 double-balanced mixers, one early, one for the real demodulator, and one late, and use those signals to control the VCXO which is your 1 MHz chip clock oscillator.

I hope this helps - if not, ask a more specific question & I'll try to understand what you need.

Good Luck!

Hi ,
Thanks a lot for your informative reply.
here is the scheme i want to implement
(1)I will have a PN code of transmitter with clock speed of 1 MHz and same clock will be provided to one control circuit which will turn on PNcode 2 (receiver) with a delayed version of PN code 1.
(2) both the PN code will be exored and the o/p is fed to Integrator and Dump circuit.
(3)the o/p of Integrator and Dump circuit will be given to thresold detector(Lm311) and o/p of this thresold detector goes to Control circuit.
here in control circuit i need a control signal which turns on the control circuit every 127microsecondsn
the timing circuit produces a pulse of 1 us(microsecond) at every 127us(since i am using 7 bit LFSRso 127 bit long PNcode.
(4)this timing circuit would turn on and off the PN code 2 (receiver)and it will reset the integrator(dump control)

so this is the scheme i wantto implement,
but i dont know how can i built Integrator and Dump and Timer circuit to produce a pulse of a desired frequency.

and what should br my control circuit to make the PN code 2 delayed version of pn code 1 ?(PN code 2 should be delayed by 1 bit)
I do have a block diagram but i dont know how can i send it to you.

Have a gr8 time
Harry


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Guest
Post subject: SyncPosted: Thu Nov 10, 2005 1:33 am
Let me see if I understand correctly. It sounds like you're saying that
1. the transmitter and receiver are co-located, so that
2. both the receiver and the transmitter linear feedback shift registers are running from the same clock, and
3.a control signal from the transmitter moves to the receiver separately from the PN sequence.

This doesn't feel right - I think I've misunderstood. Even if you're doing a detection or ranging system (like a radar), the propagation delay would act to de-synchronize the received PN code. Besides, you said that there was a data rate - which implies that you're moving data from one point to another.

For your purposes, delay comes in two varieties: sub-chip (that is, less than 1 microsecond) and integer-chip (integer number of 1 MHz cycles). A sliding correlator can handle both aspects.

Good Luck!


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Harry
Post subject: Re: SyncPosted: Thu Nov 10, 2005 6:54 pm
Guest wrote:
Let me see if I understand correctly. It sounds like you're saying that
1. the transmitter and receiver are co-located, so that
2. both the receiver and the transmitter linear feedback shift registers are running from the same clock, and
3.a control signal from the transmitter moves to the receiver separately from the PN sequence.

This doesn't feel right - I think I've misunderstood. Even if you're doing a detection or ranging system (like a radar), the propagation delay would act to de-synchronize the received PN code. Besides, you said that there was a data rate - which implies that you're moving data from one point to another.

For your purposes, delay comes in two varieties: sub-chip (that is, less than 1 microsecond) and integer-chip (integer number of 1 MHz cycles). A sliding correlator can handle both aspects.


Good Luck!


Hi ,
Is there any way to send you a block diagram?
I think that can give a better idea.

As i mentioned in the last email the scheme is as follow

I am just treing to synchronise 2 PN code
i am not using aby other data.(so no spreading of spectrum)
I just want to lock 2 PN codes .
and for that I need to generate a delay of 1 bit for 2nd PN code and i want to exor this 2 PN code and then i will integrate this exored o/p.
this integretion takes place for 127 micro seconds if my PN code is 127 bit long and runing at 1MHZ clock frequwncy.So after 127 microsecond integretor output will be dumped using some switch.

meanwhile the o/p is compared with the thresold detector.(comparator)
this thresold detector determines whether i can lock 2 PN code or not.

I dont know rest of the things and i dont know how can i generate delay of exact 1 bit for PNcode2 ( receiver Pn code.)

I also dont have much Idea what is integrator and dump ciruit.

So i request you to send me email id iso that can forward you the block diagram.

Thanks a lot

Harry


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Kirt Blattenberger
Post subject: Re: SyncPosted: Thu Nov 10, 2005 9:47 pm

Site Admin


Joined: Sun Aug 03, 2003 2:02 pm
Posts: 308
Location: Erie, PA
Harry wrote:
Hi ,
Is there any way to send you a block diagram?
I think that can give a better idea.


Greetings Harry:

If you have your block diagram online in an image format (JPG,GIF, BMP), you can display it in your post by placing the full URL to the image between as follows.

[img]URL[/img]

_________________
- Kirt Blattenberger
RF Cafe Progenitor & Webmaster


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Kirt Blattenberger
Post subject: Posted: Fri Nov 11, 2005 7:49 pm

Site Admin


Joined: Sun Aug 03, 2003 2:02 pm
Posts: 308
Location: Erie, PA
Greetings:

I don't normally do this, but Harry sent a block diagram so I uploaded it for him.



_________________
- Kirt Blattenberger
RF Cafe Progenitor & Webmaster


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Guest
Post subject: SyncPosted: Sat Nov 12, 2005 3:19 pm
Thanks for the block diagram. I have to assume that there's an RF link in there somewhere, that makes the use of an integrate-and-dump circuit desirable or necessary. Are the 2 PN shift registers co-located? (That is, are they close enough to be driven from the same physical clock line?)

As a related question, is there a sub-microsecond delay anywhere in this diagram?

Thanks, and
Good Luck!


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Harry
Post subject: Re: SyncPosted: Sun Nov 13, 2005 4:29 am
Guest wrote:
Thanks for the block diagram. I have to assume that there's an RF link in there somewhere, that makes the use of an integrate-and-dump circuit desirable or necessary. Are the 2 PN shift registers co-located? (That is, are they close enough to be driven from the same physical clock line?)

As a related question, is there a sub-microsecond delay anywhere in this diagram?

Thanks, and
Good Luck!


Hi,

yes both PN codes are located on same bench,

I am just trying to lock this 2 PN codes.
both are running at 1 MHz clock,the only difference is that the 2nd PN code is delayed by 1 clk period.(1 micrsecond).( that i want to know how can i achieve this?)

so the difference between rising edge of both the clock is 1microseond.

and one more question what should be the integrator and dump circuit ?
is there any IC for that?


Thanks
Harry.


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Guest
Post subject: SyncPosted: Sun Nov 20, 2005 2:09 am
Sorry for the delay - I've been sick - and that's gotten me behind on other stuff.

One way to get a pulse once per 127 bits is just to AND all 7 bits in the shift register.

One way to synchronize two registers is to take the AND of all 7 bits in one SR and use that to preset all the FF's in the second SR. (You'll obviously get different results with synchronous and asynchronous preset!)

A delay of one clock cycle is usually just a single flip-flop.

Integrate-and-dump circuits often require some pretty low-on-resistance FET switches - so usually people implement them with an opamp and a FET reset switch across the integrator capacitor. If memory serves, National Semi (www.national.com) has a circuit for an integrate-and-dump in many of their opamp data sheets, and may have an app. note on the subject. Also try Analog Devices (www.analog.com) and Vishay/Siliconix (V/S for FET switches).

I still don't get the feeling that I'm giving you what you want - sometimes I feel like a "bear of very little brain"...

Good Luck!


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Harry
Post subject: Re: SyncPosted: Thu Nov 24, 2005 3:37 am
Guest wrote:
Sorry for the delay - I've been sick - and that's gotten me behind on other stuff.

One way to get a pulse once per 127 bits is just to AND all 7 bits in the shift register.

One way to synchronize two registers is to take the AND of all 7 bits in one SR and use that to preset all the FF's in the second SR. (You'll obviously get different results with synchronous and asynchronous preset!)

A delay of one clock cycle is usually just a single flip-flop.

Integrate-and-dump circuits often require some pretty low-on-resistance FET switches - so usually people implement them with an opamp and a FET reset switch across the integrator capacitor. If memory serves, National Semi (www.national.com) has a circuit for an integrate-and-dump in many of their opamp data sheets, and may have an app. note on the subject. Also try Analog Devices (www.analog.com) and Vishay/Siliconix (V/S for FET switches).

I still don't get the feeling that I'm giving you what you want - sometimes I feel like a "bear of very little brain"...

Good Luck!



Hi ,
Thanks for the reply.
I still did't get how can i generate a pulse which has a TON=1 microsecond and TOff =127 microsecond.?

Could you please elaborate it ?

I tried differnt ways like IC 555 but didnt get success coz duty cycle is very less 0.78% (1/128)
I tried to play with counters but haven't got any sucess with that as well.



2 PN codes are different module here than that of test clock which has Ton=1 micrsecond and Toff =127 microseconds.

Thanks
Harry.


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Guest
Post subject: SyncPosted: Thu Nov 24, 2005 11:35 am
Assuming

1. that you're using the "classic" PN generator (a shift register with exclusive-OR gate(s) for feedback),
2. with a 1 MHz clock (= 1 microsecond)
3. that's 7 stages long,

the PN sequence will go through each possible state (a specific pattern of bits in the flip-flops making up the shift register) exactly once every 127 clock pulses. The cycle of states repeats every 127 clock pulses, so all you have to do is detect one state - I suggested the all-ONE state, because that's easy to decode using only an 8-input NAND gate, which is readily available. That gives you a pulse which is LOW for 1 microsecond and HIGH for 127, so an inverter will be needed to get what you want.



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