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substrate via in SiGe BiCMOS/CMOS - RF Cafe Forums

Because of the high maintenance needed to monitor and filter spammers from the RF Cafe Forums, I decided that it would be best to just archive the pages to make all the good information posted in the past available for review. It is unfortunate that the scumbags of the world ruin an otherwise useful venue for people wanting to exchanged useful ideas and views. It seems that the more formal social media like Facebook pretty much dominate this kind of venue anymore anyway, so if you would like to post something on RF Cafe's Facebook page, please do.

Below are all of the forum threads, including all the responses to the original posts.


dipak
Post subject: substrate via in SiGe BiCMOS/CMOS Posted: Mon Dec 18, 2006 8:08 am

Captain

Joined: Tue Nov 14, 2006 7:21 pm
Posts: 9
Location: Nagpur(M.S)
Are there any substrate vias in SiGe BiCMOS/CMOS process for grounding?

If not how should we provide groundung to the layout?


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jom
Post subject: Posted: Fri Jan 26, 2007 2:43 am

Captain


Joined: Fri Jan 26, 2007 2:40 am
Posts: 14
Are there any substrate vias in SiGe BiCMOS/CMOS process for grounding?

I would hope so.

If not how should we provide groundung to the layout?

You can use substrate ties to provide ground to the (usually) p- substrate and/or use I/O pins to ground the chip. Using plenty of substrate ties can also help prevent latch-up in certain cases if high currents are involved.

jom







Posted  11/12/2012
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