simulation of an impedance step, Transistor -> Match Net. - RF Cafe Forums
Because of the high maintenance needed to monitor and filter spammers from the RF Cafe Forums, I decided that it would be best to just archive the pages to make all the good information posted in the past available for review. It is unfortunate that the scumbags of the world ruin an otherwise useful venue for people wanting to exchanged useful ideas and views. It seems that the more formal social media like Facebook pretty much dominate this kind of venue anymore anyway, so if you would like to post something on RF Cafe's Facebook page, please do.
Below are all of the forum threads, including all the responses to the original posts.
Post subject: simulation of an impedance step, Transistor -> Match Net. Posted: Fri Apr 28, 2006 1:23 pm
Joined: Fri Apr 28, 2006 1:09 pm
I wonder how to simulate follwing condition correctly:
I have a Transistor with a connection lead of 12 mm width.
My first matching element has a width of 23mm.
I have a large signal model of the transistor for my simulator (ADS).
Das anyone konw, how to simulate the behaviour correctley?
Transistor -> Microstripline (width 23mm),
Transisor -> Impedance Step (12mm -> 23mm) -> Microstip (23mm)
Both simulatons show different results.
Would be happy for the comments from you.
Post subject: Posted: Fri Apr 28, 2006 3:43 pm
Joined: Mon Jun 27, 2005 2:02 pm
The second option which you mentioned, namely to use an impedance step is the right one. Of course that both simulations show different results, because you have a discontinuity in the impedance if you don't use an impedance step, and therfore you get an impedance mismatch and poor return loss.