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puls reshaper - RF Cafe Forums

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Below are all of the forum threads, including all the responses to the original posts.


Extreme
Post subject: puls reshaper Posted: Sat Apr 28, 2007 5:08 pm

Captain


Joined: Sun Feb 04, 2007 2:58 pm
Posts: 9
Hi all,

Let me tell you what circuit i need.
I am working on a transmitter with very lage fets.
It is a push-pull design,where the fets are going te be driven by fet drivers.
So i need 2 ttl signals
1 in phase,and 1 180 degrees out of phase.(3.5-7MHz)
The push-pull design is class E,so i need a perfect 50% duty-cycle.

Just got a DDS with a on board schmitt-trigger for creating asquare wave.
But this has ofcourse no 50% duty-cycle.
My knowlidge of logic components is only very basic,so i can not design a circuit myself.

Anyone who can give give some ideas?
Thanks a lot!


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nubbage
Post subject: Posted: Mon Apr 30, 2007 10:40 am

General


Joined: Fri Feb 17, 2006 12:07 pm
Posts: 218
Location: London UK
Hi
The way this is usually done is to run the clock at twice the desired output frequency using the usual feedback gate arrangement in TTL (74LS). That generates a logic clock at 2*F
Then drive a D-Type toggle in 74LS, and the output will be at F, with a mark space ratio of 1:1, with very little width error.
BTW: the load capacitance of high power FETS at HF is high and so you will need a large load driving current capability in the drivers. (I = dQ/dT)


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Extreme
Post subject: Posted: Mon Apr 30, 2007 2:31 pm

Captain


Joined: Sun Feb 04, 2007 2:58 pm
Posts: 9
Thanks for your reply Nubbage!

I understand the concept now.
First double and the split.

The last part of splitting with a D flip-flop is no problem.
Just played with it last week.

But can you descibe the part of doubling a little more?
Or maybe a link with an example?

You are right about the drive current of the fets.
I use very large fets...FQA11n90 with high capacitance at the gate.
Just got some IXDD414(TO220) from the USA,they should do the job.
1 driver could drive 2 fets at 3.5MHz and 1 driver/fet for 7MHz.
The class E goeroe from classeradio.com did it so it has to work

Bert


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nubbage
Post subject: Posted: Tue May 01, 2007 4:36 am

General


Joined: Fri Feb 17, 2006 12:07 pm
Posts: 218
Location: London UK
Hi extreme
If your output bit rate is critical, and you have some sort of reference clock, then phase-lock a feed-back gate clock generator to that reference, but running at 2*F. If rate is not critical, then just free-run the 2*F clock. It could be any of a range of feed-back type NAND gate pulse generators in TTL 74LS gates. When the output is fed into a D-type flip-flop, on the D port (or maybe the clock port, I can't recall the exact arrangement) then you get 1*F output with an exact 1:1 M/S ratio.
I have a logic circuit somewhere here, and I will look it out, scan it, and upload it later today. I have seen this used for a 3.5MHz Weaver type SSB transceiver, in an RSGB (UK) publication "Radcom".


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IR
Post subject: Posted: Tue May 01, 2007 3:40 pm

Site Admin


Joined: Mon Jun 27, 2005 2:02 pm
Posts: 373
Location: Germany
JKFF (JK Flip Flop) in which both J and K are tied to '1' will divide the frequency by 2.

This arrangement is called T (Toggle) FF

Here is an example:

http://hyperphysics.phy-astr.gsu.edu/hb ... pflop.html

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Extreme
Post subject: Posted: Fri May 18, 2007 1:52 pm

Captain


Joined: Sun Feb 04, 2007 2:58 pm
Posts: 9
Thought i had it ....for very short time

I made a doubler from a 74hc86 XOR(quad)
Used 3 for a delay,and the last for doubler.

Followed by a 74HC74 D-flipflop,also worked fine as a divider.

But no 50% duty-cycle....got the same signal back

Now i see the problem,the pulses out of the XOR do not start at the same period.
So the flip-flop toggles me almost the same signal back.

Anyone other options to get me 50% duty-cycle?

Greetings Bert


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nubbage
Post subject: Posted: Wed May 30, 2007 9:45 am

General


Joined: Fri Feb 17, 2006 12:07 pm
Posts: 218
Location: London UK
Hi Extreme
I have found one of my circuits buried in the archive her at Nubbage Labs, one that uses a JK flipflop rather than a D type.
Tie the J and K together to the positive supply as an enable.
Feed the double frequency into the clock input, and look at the signal on Q or Not Q.
The other circuit uses a D type FF. The 2*F circuit is just as you have done, with 4xXOR, then the output of this feeds the clock line of the FF, the Not Q feeds the D input, and the output at F is taken from the Q output with a 1:1 MS ratio.
That's what the original designer said, anyway. This came from a Electronic Design Ideas magazine.
I will look for more.


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nubbage
Post subject: Posted: Wed May 30, 2007 9:49 am

General


Joined: Fri Feb 17, 2006 12:07 pm
Posts: 218
Location: London UK
After thought: maybe you need to follow the first D type with a second D type connected as before, Not Q to D and output of previous D FF to the clock line..





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