breakdown voltage and biasing?? - RF Cafe Forums
Because of the high maintenance needed to monitor and filter spammers from the RF Cafe Forums, I decided that it would
be best to just archive the pages to make all the good information posted in the past available for review. It is unfortunate
that the scumbags of the world ruin an otherwise useful venue for people wanting to exchanged useful ideas and views.
It seems that the more formal social media like Facebook pretty much dominate this kind of venue anymore anyway, so if
you would like to post something on RF Cafe's
page, please do.
Below are all of the forum threads, including all
the responses to the original posts.
Post subject: breakdown voltage and biasing?? Posted:
Thu Dec 29, 2005 12:36 am
like kris i am also designing a PA but
it much simpler and is single ended all the way! my thing is a on-chip
PA not on a PCB. i have to worry about high voltage swing because it
is a PA and transistor breaking down. in bjt the design manual of the
technology i am using says that breakdown voltage of collector-emitter
(BVCEO) is 4 volts although the process is 5 V process (5V power supply).
i thought BVCEO is always greater than the supply voltage but here it
is not the case, any idea way?
HERE IS THE MAIN QUESTION: if
the VCE breakdown is 3.5 voltage does it mean that i CANNOT bias the
transistor across collector-emitter higher than 3.5 V? like ac swing
can go higher than BVCEO 'n i understand that but as far as DC biasing
is concerned i'm very confused...if i bias at VCE = 3.5 V than the ac
swing will be only 2*3.5 = 7 V instead of what i though should be (2*VCC
= 2*5 = 10 V)....respond pleeeease!!
Post subject: VCEPosted: Thu Dec 29, 2005 8:21 am
than you feared.
BVCEO is the maximum allowable Voltage from
the Collector to the Emitter, with the base Open - which is not normally
how you use the device.
A "5 Volt" process is one which can withstand
power supply voltages of 5 Volts - not all of that can necessarily appear
from the collector to the emitter, as you have discovered with your
"3.5 Volt VCE" rating.
So your absolute maximum swing at the
collector is from 0 to 3.5 V, That's only 3.5 V peak-to-peak, not 7
You'll need to work at a lower impedance level than you thought
- more current, less voltage. Impedance matching will be a necessary
part of such a design. If lowering the impedance can't be done then
you'll need to pick a different process.
Post subject: Posted:
Thu Dec 29, 2005 4:30 pm
so you are saying i can't bias at 3.5 VCE??
i will have to bias it as like 1.5 V? thanks for your help!!
Post subject: VCE etcPosted: Fri Dec 30, 2005
Yes. You should not ever have a voltage that exceeds 3.5
V between the collector and the emitter, if that's what the VCE(max)
rating of the transistor is. For class A operation, that implies a DC
bias point near 1.5 Volts.
What happens if you exceed 3.5V from
collector to emitter?
If you exceed it too much, you get instantaneous
failure (we've all done it!) However, if you exceed it by a little,
you're gambling on process statistics and long-term reliability.
Posted: Fri Dec 30, 2005 1:56 pm
hi...thanks a lot. but let me clarify
something. i have couple of books that cover PAs and in all of them
they show that the output voltage waveform (vc or vce waveform) is centered
around VCC (because of the RFC inductor at the collector, i think) which
would mean that they are biasing the transistor at the supply voltage!!!
doesn't make sense to me...maybe they are assuming that their VCE breakdown
is higher than the supply voltage, could that be the case?
if the above is true and i also use a RFC then my 5V supply will go
across collector-emitter and since my BVCEO is only 3.5, this means
breakdown. do i not use RFC?? please clarify if possible...thanks
Post subject: Posted: Tue Jan
03, 2006 8:44 pm
BVceo is a very conservative number because as
guest says it is not how you normally use the device.
the maximum allowable Voltage from the Collector to the Emitter, with
the base Shorted. BVces is usually much larger than BVceo and approaching
that limit requires sinking all consequent base current to the emitter.
What you can get away with is between those two numbers. Also, pushing
these limits can cost you some noise floor because break down is very
The news gets much worse for a PA when VSWR is taken
in to account. If you are pushing the limits with a well matched Class
A, there is a mistermination phase that will likely push the peak to
peak voltage towards twice its terminated value.
Use the RFC
but not the 5V process.