VCO,Packaging model and ESD [help] - RF Cafe Forums
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Post subject: VCO,Packaging model and ESD [help] Posted: Wed Jul 27, 2005 6:13 am
Joined: Mon May 24, 2004 11:30 pm
In above figure, Lg means the packaing's
parasitic inductor(e.g.,~2nH in 128pin QFP) and Cp means ESD and bond pad's parasitic capacitor(e.g.,~3pF). It
means that this LgCp tank's resonance frequency is about 2GHz.
Unfortunately, the frequency of my signal
from Port1 is just about 2GHz(it is a VCO signal and vary from 1.8GHz to 2.2GHz). Even when my signal's
peak-to-peak voltage value is 0.4v, the simulation shows that the peak-to-peak voltage value at Port2(it is the
gate of a NMOS) is about 10v(my vdd is 2.5v). It will make the NMOS breakdown!
In theory,I found that if
the LgCp's res. freq.(i.e.,1/sqrt(Lg*Cp)) equal the signal's frequency, the signal at Port2 will be large very
How to solve this problem? Would you please give me any advice or references?
Post subject: Posted: Wed Jul 27, 2005 6:25 am
Joined: Mon Jun 27, 2005 2:02 pm
Just a comment: The
resonance frequency equals -
It will make the resonance frequency even lower.
Please provide more details about your circuit.
Post subject: Posted: Wed Jul 27, 2005 9:46 am
May 24, 2004 11:30 pm
Nice to see you again.
I want to introduce an external VCO
signal(about 2GHz) into my circuit(a divider) in order to realize a frequency synthesizer.(i.e.,the vco in this
frequency synthesizer is external,not in my die).
So I add the packaing model(it is a 4-port model for vco
differential siganl) and sweep the Cp(acted as the 100um*100um bond pad's capacitor and ESD capacitor) in the
schematic of my first post. Then connect with my divider(i.e.,Port2 is connected with my divider).
input siganl(at Port1 in the schematic in my first post) peak-to-peak voltage is 0.4v,I found the Port2's voltage
increase from about 0.5v to 15v with the increasing Cp from 0p to 2p. Then Port1 voltage will decrease to 0.1v
with continually increasing Cp from 2p to 10p. In other words, the peak-to-peak voltage value at Port1 have a peak
value(about ~15v) and this peak value exists when input signal's frequency close to the LgCp tank's resonance
frequency. I am afraid that such a large voltage will demage the MOS in divider practically. Seriously it will
make my divider out of work!
IR,is there any similar phenomenon in RFIC circuit? for example, when use a
off-chip RF PLL to provide LO signal for mixer(because in this situation, a RF LO signal has to be introduced into
mixer and this signal must be affected by mixer's packaging and ESD). How to handle this situation?
you very much.
Post subject: Posted: Wed Jul 27, 2005 10:29 am
Joined: Mon Jun 27, 2005 2:02 pm
have experience in RFIC design, however I can tell you that in any PLL synthesizer that I saw or designed myself,
I used to connect a pad (Resisitive element) between the divider's input and the VCO output in order to provide
match to the divider's input and to adjust the level of the power from the VCO into the divider. I don't know if
this is possible in your design. This pad has no capacitive effect, since it is composed of resistors, why don't
you give it a go?
Post subject: Posted: Wed Jul 27, 2005 8:57 pm
Joined: Mon May 24, 2004 11:30
I will use an attenuator between the divider and vco in order to do
impedance match,power match and bias voltage. I am not sure whether such a resistive netwoek will help me.
Thank you again.