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Post subject: Spurs problem in Synt. caused by Vcc pll voltage
Unread postPosted: Wed Jul 06, 2005 8:57 am
I've encountered a spur problem in my design and I’m trying to figure it out but without any luck, and I hoped someone here will be able to assist me.
My design problem is as follows:
I've designed a synthesizer from 720-790MHz and I'm using ADF4118
to lock the desired frequency. The thing is that when I change the Vcc PLL voltage by 0.1v from 5 to 4.9 or 5.1 there is a significant degradation in the comparison spur performance from -92 dBc to -72 dBc.
The loop parameters are: Phase Margin: 39 deg.
Loop Bandwidth: 3.79 KHz.
Last pole location: 66.1 KHz.
Step size: 100 KHz.
Ref. freq.: 10MHz.
I’m using three stages, passive loop filter.
Unread postPosted: Thu Jul 07, 2005 3:55 pm
Joined: Mon Jun 27, 2005 2:02 pm
First you can design your loop filter by Analog Devices ADISIM PLL (If I remember correctly its name). It is a similar tool as National's WEBENCH
I believe that the cause of the problem you described is in the connection of the supply voltage. From your description it sounds that you use a single voltage source for both of these supplies. You should use 2 different supplies one for the AVdd and the other for DVDD. The 2 different supplies AVdd and DVdd are for the Analog and Digital sections within the IC respectively and they should come from different regulators. It seems that there is an interaction between Aanlog and Digital sections in the IC that happens due to common supply voltage!
To provide good filtering (Which is very important in PLL Synthesizers), you should connect several values of bypass capacitors (and also a Ferrite Bead if possible) to provide a good noise filtering.
Also check that your reference source (probably a TXCO) is filtered adequately. :!:
Good luck! should you need more help, let me know :)