Because of the high maintenance needed to monitor and filter spammers from the RF Cafe Forums, I decided that it would
be best to just archive the pages to make all the good information posted in the past available for review. It is unfortunate
that the scumbags of the world ruin an otherwise useful venue for people wanting to exchanged useful ideas and views.
It seems that the more formal social media like Facebook pretty much dominate this kind of venue anymore anyway, so if
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Below are all of the forum threads, including all
the responses to the original posts.
Post subject: Power FET question Posted: Fri Apr 21, 2006 10:42
Joined: Fri Apr 21, 2006 10:34 pm
hi...i am student and this is simple question: i have a power
fet that need to be biased at 12 A of current for its Id biasing.however
the current source outputs 25 A of current. since i don't have resistor
that can handle this level of current what can i do so that only 12
A of current goes in the drain of the current? thanx
Post subject: Posted: Mon Apr 24, 2006 4:07
Joined: Mon Jun 27, 2005 2:02 pm
The current passing
through the FET's drain is set by the minimal load that you will connect
to your circuit. There are many current limiting circuits relatively
easy to implement, and you need to use one in your design. Look in Google
there are many applications for such circuits.
Here is just
a single example from a quick search in Google:
Posted: Tue Jun 13, 2006 10:21 pm
Tue Mar 15, 2005 11:43 pm
I agree with IR.
Antoher way to control the drain current,
you also may want to limit/set your gate biasing voltage, so that it
will give you the desired drain current at respective drain voltage.
For doing this, you can try to apply voltage divider in the gate bias
I hope it helps.