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PLL phase coherence - RF Cafe Forums

Because of the high maintenance needed to monitor and filter spammers from the RF Cafe Forums, I decided that it would be best to just archive the pages to make all the good information posted in the past available for review. It is unfortunate that the scumbags of the world ruin an otherwise useful venue for people wanting to exchanged useful ideas and views. It seems that the more formal social media like Facebook pretty much dominate this kind of venue anymore anyway, so if you would like to post something on RF Cafe's Facebook page, please do.

Below are all of the forum threads, including all the responses to the original posts.


Guest
Post subject: PLL phase coherence Posted: Mon Jan 23, 2006 1:56 pm
Hi all,

Just wondering if anyone has any methods of getting 2 PLLs, which are running off the same reference, to have the same RF phase?

thanks


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r
Post subject: Posted: Mon Jan 23, 2006 4:00 pm
Everthing else being equal you should be in phase. The higher you go in freq the less this is true, due to mismatch of the VCO.


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guest
Post subject: Posted: Tue Jan 24, 2006 8:24 am
differences in leakage currents between the PLLs?


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Guest
Post subject: PLL phase matchingPosted: Tue Jan 24, 2006 3:34 pm
1. You'll want a real third-order loop, to force the phase error at the detector to zero and keep it there. See PLL books such as Gardner's classic.
2. The two loops should be physically identical, and equidistant from the reference and the point where the output phase difference is measured. (Assuming a UHF/microwave PLL - you weren't very specific).

Good Luck!


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guest who asked
Post subject: Posted: Wed Jan 25, 2006 1:14 pm
thanks for your suggestions, but if there are leakage currents, then no amount of filtering will remove them. a 10uA leakage current will flow regardless of whether you use a 2nd, 3rd or 4th order loop filter. The charge pump will then force a phase error at the PFD inputs...

RFout is in the 1-5GHz range, PFD's of the order of 1-20MHz.


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guest
Post subject: PLLPosted: Wed Jan 25, 2006 8:59 pm
Leakage currents are controllable, so they can be reduced - almost always to negligible levels, given modern FETs. Whether or not you want to go to the effort is your choice. Still, you're using multiplication ratios in the 1000-5000 range, so phase error at the PFD would have to be tiny.
At that point, many PFD's have dead-zone and transition-time issues. So I wouldn't count on the phase matching too closely.

So I agree with your pessimism, "guest who asked".

Good Luck anyway!


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guest who asked
Post subject: Posted: Thu Jan 26, 2006 7:59 am
thanks for replying. yes that's why im pessimistic. If one part heats up by 10 degrees and the other doesn't, the leakage current would double in the higher temp one. Depending on N divide ratios/ base leakage currents, it could translate to a huge phase difference at RF.


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Guest
Post subject: Posted: Thu Jan 26, 2006 2:02 pm
I do not understand very well the involvment of PLL leakage current in the process of generating a phase error.

From my understanding, even a second order loop under a fixed reference signal, would give no phase error if we look at the closed loop phase error transfer function evaluated at T= ininite.

I the phase is different the charge pump will generate a pulse every cycle, the only condition driving to no pulse is a very small jitter around perfect phase. As far as we are concerned about what is going on in the loop, the phase must be exact

Under a moving phase reference then only a 3rd order loop makes the job from what I read but that is another question.

I see more the other facter around the PFD to Charge pump section to be contributiing to the error (reference conditionning circuitry, LO amplificatoin circuitry, and tranmsission lines exlectrical lenght variation due to whatever factor will indeed deteriorate the phase error.

I am missing something regarding charge pump leakage current?



Posted  11/12/2012
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