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| PLL Phase margin - RF Cafe Forums | ||||||
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Because of the high maintenance needed to monitor and filter spammers from the RF Cafe Forums, I decided that it would
be best to just archive the pages to make all the good information posted in the past available for review. It is unfortunate
that the scumbags of the world ruin an otherwise useful venue for people wanting to exchanged useful ideas and views.
It seems that the more formal social media like Facebook pretty much dominate this kind of venue anymore anyway, so if
you would like to post something on RF Cafe's
Facebook page, please do.
Below are all of the forum threads, including all the responses to the original posts. Noise Post subject: PLL Phase margin Posted: Sun Oct 14, 2007 6:42 am Captain Joined: Tue May 02, 2006 4:59 am Posts: 15 Hi all, I am looking for good explanation about phase margin and its relation to PLL stability. Why 45 degree is optimum ? Thanks in advance, Noise Top IR Post subject: Posted: Tue Oct 16, 2007 12:14 am Site Admin Joined: Mon Jun 27, 2005 2:02 pm Posts: 373 Location: Germany Phase margin of 45 deg. is a good compromise between the lock time of the loop and an adequate loop stability. Phase margin is defined as 180deg minus the phase of the open loop, at the frequency of the loop bandwidth. For detailed explanation about phase margin and other PLL related topics, you can read in the following line: http://www.national.com/appinfo/wireles ... nbook.html Posted 11/12/2012 | ||||||
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