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| Modeling Printed Circuit Board Parasitic Capacitances - RF Cafe Forums | ||||||
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Because of the high maintenance needed to monitor and filter spammers from the RF Cafe Forums, I decided that it would
be best to just archive the pages to make all the good information posted in the past available for review. It is unfortunate
that the scumbags of the world ruin an otherwise useful venue for people wanting to exchanged useful ideas and views.
It seems that the more formal social media like Facebook pretty much dominate this kind of venue anymore anyway, so if
you would like to post something on RF Cafe's
Facebook page, please do.
Below are all of the forum threads, including all the responses to the original posts. Michael Post subject: Modeling Printed Circuit Board Parasitic Capacitances Posted: Tue Oct 25, 2005 11:51 am Good day. When I have simulated circuits I always had to add the parasitic capacitances (from the printed circuit board) manually to my simulation. This got to be a very time consuming process particularily if the circuit was large. I am looking for some information (book, magazine, website, personal experience, etc.) about how to determine the parasitic capacitance. When I have done a literature search, most of the articles that I find discuss building test boards and measuring the components, then extracting the parasitics. I do not want to use this method because it is time consuming. Also the models are only valid for one type of circuit board (i.e. one substrate thickness and one dielectric constant, etc.) Thank you for your time and help. Michael Posted 11/12/2012 | ||||||
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