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Below are all of the forum threads, including all
the responses to the original posts.
Post subject: Low device impedance
Tue Apr 05, 2005 10:19 pm
Hi All :
I'm dealing with low-impedance
FET for power amplifier design.
I realized that at some gate voltage
biasing point, the IM3 balance performance (between IM3 high and IM3
low) is worse, while the absolute IM3 value is better.
tried lower gate voltage IM3 balance is improved, same as when I tried
higher gate voltage. So means, at only this gate voltage, the phenomenon
I guess it's probably canceling out phenomenon of the
I am not sure about this.
and also I observe this low-impedance
device is very sensitive to gate voltage, instead of current.
I mean even though the drain current different by 15mA to 20 mA,
the IM3 differs a lot, at this gate voltage.
Could you enlighten
me in this issues?
will appreciate your advice :wink:
Unread postPosted: Tue Apr 05, 2005 11:52
I found out a similar phenomenon in my
power amplifier which is based on LDMOS technology (Enhancement MOSFET),
this phenomenon is called" sweet point" meaning the gate voltage level
that gives you the best IM3 performance. If you go around this point
you will se that IM3 degrades, so this is a singular level. RF power
amplifiers manufacturers use to measure that level at various temperatures
and design the bias circuit to give that voltage and closing a loop
over it to maintain the bias level over temperature.
has of course to do with the intrinsic structure of the device.
Unread postPosted: Wed Apr 06, 2005 1:02 am
Thank you for your
By the way, I'm not sure whether I
could say LDMOS as low-impedance device? I'm not familiar with this
LDMOS device as currently I'm using GaAs MESFET.
appreciate if you could give me some information / white papers on this
LDMOS sweet point issue. :wink:
Thank you so much.
Wed Apr 06, 2005 1:39 am
You can find useful
information on LDMOS on Google Search. I am sorry, but I never invesitigated
this issue thorughly.
The prominent manufacturer of LDMOS transistors
LDMOS are widely used for Cellular/UMTS/PCS bands,
i.e. 800-2100MHz, however there are lower frequecies models down to
What is your frequency band?
By the way, as higher
the output power the device is capable to as lower its output impedance
Hope this helps.
Unread postPosted: Wed Apr 06, 2005 9:58 pm
Thanks again for your advice.
frequency band is 1.8GHz.
I am wondering whether this phenomenon
that appears in MESFET, is mostly happened at low-impedance MESFET?
Because I did not experience this at higher impedance MESFET. I
am not sure about this.
Could anybody enlighten me? :wink:
Thank you so much.
Unread postPosted: Wed Apr 06,
2005 11:47 pm
It happens in higher impedance devices
as well. It is a common phenomenon in these devices. The best way to
observe this phenomenon is to move up and down with the gate voltage
around this point, do that and you should see how IM3 products goes
up and then up again around a singular minimum extremum point.
Can you give more details about your application? like output power?
Do you use some sort of linearizer?
Anyway, I have done comparisons
of efficiency and linearity between LDMOS and GaAs FET at your band
too. The LDMOS technonlogy leaves the GaAs FET way behind both at linearity
You can write to me too: email@example.com
Hope this helps