Because of the high maintenance needed to monitor and filter spammers from the RF Cafe Forums, I decided that it would
be best to just archive the pages to make all the good information posted in the past available for review. It is unfortunate
that the scumbags of the world ruin an otherwise useful venue for people wanting to exchanged useful ideas and views.
It seems that the more formal social media like Facebook pretty much dominate this kind of venue anymore anyway, so if
you would like to post something on RF Cafe's
page, please do.
Below are all of the forum threads, including all
the responses to the original posts.
Post subject: ESD HBM model Test Bench Posted: Mon Aug 31, 2009 7:33 am
Joined: Mon Aug 31, 2009 7:25 am
I am building a HBM ESD test bench and I came up
to the following question:
When I connect the ESD protection circuit and the theoretical input to the main
circuit (ie an n-MOS),
what I put as Vcc and Vee voltage of the ESD?
My original idea is to leave it
floating. But then, floating means arbitrary voltage in the power lines.
My second thought is to put both
VCC and VEE inputs to the same node which eventually is connected to the substrate.
The second approach
shows a well operating ESD protection scheme. But is it the correct one, meaning, is it the one corresponding in
the real situation?
Post subject: Re: ESD HBM
model Test BenchPosted: Mon Sep 21, 2009 10:33 pm
Joined: Sat Mar 04, 2006 10:12 am
IEC 61000-4-2 lays out all of the "official" tests for ESD testing.
Unfortunately, you have to buy the spec from IEC (not cheap):
For Military systems, the specification is MIL-STD-883, Method 3015.7 (free, compliments of taxpayers)