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4 layer Mixed Signal PCB Layout - RF Cafe Forums

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Below are all of the forum threads, including all the responses to the original posts.


emo
Post subject: Mixed Signal PCB Layout Posted: Wed Jun 07, 2006 12:58 am

Lieutenant

Joined: Wed Jun 07, 2006 12:38 am
Posts: 4
Hi all!

I am a newbie to rf design and I am currently working on a 4 layer mixed signal PCB layout that includes 2.4GHz transceiver. The layer stackup is signal-ground-power-signal.
The questions I have are are in regards to (copper fill)grounding.

1. What is the advantage of using ground (copper fill) on top layer and stitching it to other ground plane? Should I use this approach?
2. Should stitching extend to non-RF (digital) sections of the PCB?
3. Why are stitching vias usually more densly populated in some areas than in others?

Thanks in advance!


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IR
Post subject: Posted: Wed Jun 07, 2006 9:22 am

Site Admin


Joined: Mon Jun 27, 2005 2:02 pm
Posts: 373
Location: Germany
Hi emo,

I hope that you placed the RF signals in the top layer and the Digital signals in the bottom layer. A good advice is to fill as much as possible the power layer with coppr planes and stitch them to GND.

Ground fill is usually done around the RF signals of the PCB. This is part of the co-planar transmission lines. You should use this approach. The advantage is that it reduces the impedance of the ground return and makes a continuous and complete GND plane.

You can extend it also to Digital sections as much as the layout allows you.

The vias are more densed in the RF sections because the wavelength is smaller. There is a rule-of-thumb that the space between the vias should not exceed 1/10 of the signal's wavelength.

_________________
Best regards,

- IR


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checkz
Post subject: yes&#65292; i could not agree morePosted: Thu Jun 08, 2006 4:16 am
It is an useful suggesition and i can learn a lot.
thanks IR


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emo
Post subject: Posted: Fri Jun 09, 2006 1:58 am

Lieutenant

Joined: Wed Jun 07, 2006 12:38 am
Posts: 4
Thanks for your reply IR! It helped a lot, but I still have some mor equestions.
I did placed RF on top and digital on the bottom layer. You mentioned that I should fill as much as possible of power plane with copper and stitch to ground. Did you reffer to filling top layer (RF) with copper here, or am I missing something?
I have one other question.
Do you recomend using continious power plane or routing power on the power plane using wide traces? I have found lots of conflicting recomendations in regards to this.

Best Regards!


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IR
Post subject: Posted: Fri Jun 09, 2006 7:00 am

Site Admin


Joined: Mon Jun 27, 2005 2:02 pm
Posts: 373
Location: Germany
Hi emo,

You are most welcome!

I recommend to use wide power traces and to fill all the gaps between them with coppoer planes and stitching them to GND with vias.

The copper planes on the top layer are the GND, and they should be stitched with vias to the copper planes in the power layer.

If you have more questions, please post them or email them to me.

Good luck!

_________________
Best regards,

- IR


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Stephen
Post subject: Alternative thoughtPosted: Wed Jun 21, 2006 9:06 pm

Captain

Joined: Wed Jun 21, 2006 8:33 pm
Posts: 21
Location: Queen Creek, Arizona
Regarding the comments, I would like to add that depending on the nature of your power delivery/power requirements of the system, you would could be better off using a power plane as opposed to traces. Power delivery can suffer many of the impedance issues experienced by return paths in the ground planes.

Power planes can be used just like ground planes for transmission lines assuming there is adequate decapping between the two(this is great if you are routing lots of digital signals on the bottom layer as then you would not have issues with signals running over broken planes). You also avoid problems with manufacturability by having paired solid planes (though ground filling a power plane would go a long way toward this goal.)

Parallel planes also add a certain amount of intrinsic decap with very little series inductance.

Just thought I would add my 2cents.

_________________
CMOS RF and Analog ESD Specialist!
www.srftechnologies.com

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emo
Post subject: Posted: Wed Jun 28, 2006 11:02 pm

Lieutenant

Joined: Wed Jun 07, 2006 12:38 am
Posts: 4
thanks for your help guys!

I have yet one more question.
My digital section seems to be more complex than oiginaly intended so it seems impossible to route only on one layer. I tried to keep all of the digital signals on botom and RF on top layer, but it is not practical for this design.

Is it ok to route some parts of digital signals on the top plane (dedicated to RF), or should I use another layer for this?

Thanks again!


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IR
Post subject: Posted: Thu Jun 29, 2006 5:44 am

Site Admin


Joined: Mon Jun 27, 2005 2:02 pm
Posts: 373
Location: Germany
Hi emo,

Yes many times that happens. Try to route on the top layer the digital signals which have the lowest frequency or with low activity on it. In this way the RF signals will stay relatively clean. Try also to keep (As much as possible) a distance between the Digital signals to the RF signals.

Another question: How have you finally routed the signals by planes or by wide traces?

Hope this helps!

_________________
Best regards,

- IR


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emo
Post subject: Posted: Thu Jun 29, 2006 12:53 pm

Lieutenant

Joined: Wed Jun 07, 2006 12:38 am
Posts: 4
I have routed power using thick traces and filled the remainder of plane with coper connected to ground. i will stich all the grounds together.

Thanks again, your advice helped me a lot!


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Stephen
Post subject: Posted: Thu Jun 29, 2006 12:58 pm

Captain

Joined: Wed Jun 21, 2006 8:33 pm
Posts: 21
Location: Queen Creek, Arizona
Emo,
IR is correct. It is perfectly legitimate, just use those digital signals with the lowest frequency components/activity. Note, this is truly dependent on the risetime of the digital signals, and then the activity factor.

To use a very crude hypothetical example, a 32kHz Clk with a 3nS risetime can have strong energy components upto and including 166Mhz.
A 1Mhz Clk with a 10n risetime would have most of its energy under 35Mhz.
This is a crude example so nobody hold me to it, but I think the point regarding being aware of the risetime of your signals is evident when deciding which signals to route on the upper plane. One reason also to be aware of this is that the faster risetimes will generate higher peak currents in the return path of your ground plane, allowing coupling to any RF signals sharing that plane.

One trick I have used, if appropriate, is I in somecase I applied a risetime filter to certain low frequency control signals that were being implemented in ECL logic (ergo they had very fast risetimes by design). As I did not need the fast risetime for any spec of the system, by filtering it at the signal driver, I was able to keep much of my system noise down. This is if it is appropriate, I do not recommend that people start filtering digital signals left and right, imagine the board cost and space...ouch.

Ok, I will stop there.
stephen

_________________
CMOS RF and Analog ESD Specialist!
www.srftechnologies.com







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